Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26799	1			T13	7		T14	9		T16	4
auto[PWRUP]	110	1			T57	2		T56	1		T62	3
auto[ONEST_0]	59	1			T62	1		T188	1		T59	3
auto[ONEST_021]	12	1			T57	1		T55	1		T189	1
auto[ONEST_1]	74	1			T57	1		T54	3		T190	2
auto[ONEST_DONE]	3	1			T191	1		T192	1		T193	1
auto[LP_0]	115	1			T56	2		T62	2		T54	2
auto[LP_021]	17	1			T194	1		T195	1		T196	1
auto[LP_1]	128	1			T57	2		T56	1		T62	2
auto[LP_EVAL]	49	1			T62	1		T54	2		T190	1
auto[LP_SLP]	477	1			T57	4		T56	12		T62	9
auto[LP_PWRUP]	23	1			T189	1		T197	1		T194	1
auto[NP_0]	140	1			T57	2		T56	3		T62	1
auto[NP_021]	26	1			T56	1		T54	3		T55	1
auto[NP_1]	147	1			T57	2		T56	3		T62	1
auto[NP_EVAL]	24	1			T55	3		T188	1		T197	1
auto[NP_DONE]	1	1			T59	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T57

1

T188

1

T196

1

min

26348

1

T13

7

T14

9

T16

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26359	1			T13	7		T14	9		T16	4
pow[0x1]	6	1			T198	1		T199	1		T200	1
pow[0x2]	18	1			T195	2		T196	2		T201	1
pow[0x3]	27	1			T190	1		T55	1		T189	1
pow[0x4]	46	1			T57	1		T56	1		T54	1
pow[0x5]	133	1			T57	2		T56	2		T62	4
pow[0x6]	232	1			T57	5		T56	2		T62	3
pow[0x7]	476	1			T57	11		T56	9		T62	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

181

1

T57

3

T56

2

T62

4

min

25900

1

T13

7

T14

9

T16

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25900	1			T13	7		T14	9		T16	4
pow[0x5]	3	1			T190	1		T202	1		T203	1
pow[0x7]	1	1			T204	1		-	-		-	-
pow[0x8]	4	1			T205	1		T206	1		T207	1
pow[0x9]	3	1			T208	1		T209	1		T61	1
pow[0xa]	12	1			T210	2		T211	1		T204	1
pow[0xb]	25	1			T57	1		T62	1		T190	1
pow[0xc]	74	1			T57	1		T56	1		T62	3
pow[0xd]	139	1			T57	1		T56	6		T62	1
pow[0xe]	276	1			T57	3		T56	3		T62	5
pow[0xf]	512	1			T57	2		T56	9		T62	9