Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2023	1			T2	10		T21	20		T47	20
auto[PWRUP]	124	1			T11	1		T12	1		T15	1
auto[ONEST_0]	72	1			T2	1		T43	1		T62	1
auto[ONEST_021]	19	1			T11	1		T62	1		T46	1
auto[ONEST_1]	73	1			T62	3		T55	2		T188	4
auto[ONEST_DONE]	2	1			T360	1		T207	1		-	-
auto[LP_0]	133	1			T57	3		T56	3		T62	2
auto[LP_021]	26	1			T56	1		T54	1		T55	1
auto[LP_1]	119	1			T11	1		T42	2		T45	1
auto[LP_EVAL]	36	1			T54	2		T55	1		T361	1
auto[LP_SLP]	487	1			T2	1		T42	1		T44	1
auto[LP_PWRUP]	24	1			T57	1		T56	1		T55	1
auto[NP_0]	155	1			T11	2		T15	1		T42	1
auto[NP_021]	51	1			T11	1		T20	1		T55	2
auto[NP_1]	178	1			T11	2		T15	1		T20	1
auto[NP_EVAL]	22	1			T44	1		T190	1		T189	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T210

1

T362

1

T60

1

min

1668

1

T2

12

T21

20

T47

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1676	1			T2	12		T21	20		T47	20
pow[0x1]	11	1			T42	1		T195	1		T363	1
pow[0x2]	16	1			T55	1		T189	1		T59	1
pow[0x3]	34	1			T56	1		T46	1		T54	1
pow[0x4]	60	1			T56	1		T54	1		T55	1
pow[0x5]	105	1			T42	1		T57	4		T62	1
pow[0x6]	240	1			T57	4		T56	2		T62	2
pow[0x7]	475	1			T11	1		T42	1		T57	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

182

1

T12

1

T42

1

T57

2

min

1168

1

T2

12

T21

20

T47

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1179	1			T2	12		T21	20		T47	20
pow[0x1]	14	1			T11	3		T15	1		T20	1
pow[0x2]	13	1			T20	1		T43	1		T44	2
pow[0x3]	10	1			T42	1		T45	1		T163	1
pow[0x4]	14	1			T42	1		T45	1		T297	1
pow[0x6]	4	1			T60	1		T202	1		T364	1
pow[0x7]	1	1			T198	1		-	-		-	-
pow[0x8]	4	1			T196	1		T365	1		T366	1
pow[0x9]	9	1			T208	1		T205	1		T206	1
pow[0xa]	21	1			T57	1		T62	1		T54	1
pow[0xb]	31	1			T62	1		T54	2		T361	1
pow[0xc]	71	1			T11	1		T56	1		T62	3
pow[0xd]	130	1			T57	2		T56	2		T62	4
pow[0xe]	266	1			T43	1		T57	1		T56	5
pow[0xf]	560	1			T42	1		T57	2		T56	9