Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	32284838	32212917	0	0
FsmStateHwReset_A	989	989	0	0
FsmStateSwReset_A	32284838	6731	0	0
LpSampleCntHwReset_A	989	989	0	0
LpSampleCntSwReset_A	32284838	6731	0	0
NpSampleCntHwReset_A	989	989	0	0
NpSampleCntSwReset_A	32284838	6731	0	0
PwrupTimerCntHwReset_A	989	989	0	0
PwrupTimerCntSwReset_A	32284838	6731	0	0
WakeupTimerCntHwReset_A	989	989	0	0
WakeupTimerCntSwReset_A	32284838	6731	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	32212917	0	0
T1	1198	1098	0	0
T2	58	1	0	0
T3	77	1	0	0
T4	723	652	0	0
T5	7053	6993	0	0
T6	1142	1087	0	0
T7	628	569	0	0
T8	1174	1097	0	0
T21	55	1	0	0
T22	92	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989	989	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	6731	0	0
T13	39448	7	0	0
T14	33534	9	0	0
T15	453	0	0	0
T16	32908	4	0	0
T17	66788	16	0	0
T18	0	6	0	0
T19	0	23	0	0
T23	1175	0	0	0
T24	754	0	0	0
T25	73	0	0	0
T26	81	0	0	0
T27	1163	0	0	0
T40	0	10	0	0
T41	0	14	0	0
T87	0	18	0	0
T88	0	7	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989	989	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	6731	0	0
T13	39448	7	0	0
T14	33534	9	0	0
T15	453	0	0	0
T16	32908	4	0	0
T17	66788	16	0	0
T18	0	6	0	0
T19	0	23	0	0
T23	1175	0	0	0
T24	754	0	0	0
T25	73	0	0	0
T26	81	0	0	0
T27	1163	0	0	0
T40	0	10	0	0
T41	0	14	0	0
T87	0	18	0	0
T88	0	7	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989	989	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	6731	0	0
T13	39448	7	0	0
T14	33534	9	0	0
T15	453	0	0	0
T16	32908	4	0	0
T17	66788	16	0	0
T18	0	6	0	0
T19	0	23	0	0
T23	1175	0	0	0
T24	754	0	0	0
T25	73	0	0	0
T26	81	0	0	0
T27	1163	0	0	0
T40	0	10	0	0
T41	0	14	0	0
T87	0	18	0	0
T88	0	7	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989	989	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	6731	0	0
T13	39448	7	0	0
T14	33534	9	0	0
T15	453	0	0	0
T16	32908	4	0	0
T17	66788	16	0	0
T18	0	6	0	0
T19	0	23	0	0
T23	1175	0	0	0
T24	754	0	0	0
T25	73	0	0	0
T26	81	0	0	0
T27	1163	0	0	0
T40	0	10	0	0
T41	0	14	0	0
T87	0	18	0	0
T88	0	7	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989	989	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32284838	6731	0	0
T13	39448	7	0	0
T14	33534	9	0	0
T15	453	0	0	0
T16	32908	4	0	0
T17	66788	16	0	0
T18	0	6	0	0
T19	0	23	0	0
T23	1175	0	0	0
T24	754	0	0	0
T25	73	0	0	0
T26	81	0	0	0
T27	1163	0	0	0
T40	0	10	0	0
T41	0	14	0	0
T87	0	18	0	0
T88	0	7	0	0