Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2122	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2144	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1932	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1991	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1940	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1978	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2176	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2185	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2086	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2038	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2001	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1882	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2031	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2023	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2048	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2046	0	0
adc_en_ctl_rd_A	2147483647	1726	0	0
adc_fsm_rst_rd_A	2147483647	1653	0	0
adc_intr_ctl_rd_A	2147483647	1960	0	0
adc_lp_sample_ctl_rd_A	2147483647	1735	0	0
adc_pd_ctl_rd_A	2147483647	1837	0	0
adc_sample_ctl_rd_A	2147483647	1662	0	0
adc_wakeup_ctl_rd_A	2147483647	1653	0	0
intr_enable_rd_A	2147483647	1893	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2122	0	0
T11	603682	33	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	11	0	0
T29	0	35	0	0
T30	0	10	0	0
T31	0	11	0	0
T32	0	16	0	0
T33	0	40	0	0
T34	0	15	0	0
T35	0	4	0	0
T36	0	16	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144	0	0
T11	603682	52	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	34	0	0
T29	0	36	0	0
T30	0	17	0	0
T31	0	35	0	0
T32	0	9	0	0
T33	0	32	0	0
T34	0	19	0	0
T35	0	18	0	0
T36	0	29	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1932	0	0
T11	603682	43	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	21	0	0
T29	0	25	0	0
T30	0	16	0	0
T31	0	25	0	0
T32	0	20	0	0
T33	0	27	0	0
T34	0	13	0	0
T35	0	8	0	0
T36	0	26	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1991	0	0
T11	603682	18	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	18	0	0
T29	0	15	0	0
T30	0	20	0	0
T31	0	25	0	0
T32	0	16	0	0
T33	0	41	0	0
T34	0	17	0	0
T35	0	10	0	0
T36	0	24	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940	0	0
T11	603682	27	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	24	0	0
T29	0	39	0	0
T30	0	21	0	0
T31	0	23	0	0
T32	0	17	0	0
T33	0	43	0	0
T34	0	20	0	0
T35	0	13	0	0
T36	0	22	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T11	603682	43	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	9	0	0
T29	0	27	0	0
T30	0	13	0	0
T31	0	4	0	0
T32	0	11	0	0
T33	0	44	0	0
T34	0	17	0	0
T35	0	7	0	0
T36	0	15	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2176	0	0
T11	603682	36	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	10	0	0
T29	0	34	0	0
T30	0	5	0	0
T31	0	31	0	0
T32	0	15	0	0
T33	0	46	0	0
T34	0	22	0	0
T35	0	12	0	0
T36	0	21	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2185	0	0
T11	603682	26	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	23	0	0
T29	0	17	0	0
T30	0	18	0	0
T31	0	28	0	0
T32	0	18	0	0
T33	0	28	0	0
T34	0	35	0	0
T35	0	3	0	0
T36	0	17	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086	0	0
T11	603682	37	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	19	0	0
T29	0	45	0	0
T30	0	21	0	0
T31	0	30	0	0
T32	0	17	0	0
T33	0	30	0	0
T34	0	16	0	0
T35	0	4	0	0
T36	0	16	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2038	0	0
T11	603682	41	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	18	0	0
T29	0	49	0	0
T30	0	12	0	0
T31	0	20	0	0
T32	0	25	0	0
T33	0	42	0	0
T34	0	18	0	0
T36	0	14	0	0
T37	0	36	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2001	0	0
T11	603682	25	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	22	0	0
T29	0	58	0	0
T30	0	3	0	0
T31	0	10	0	0
T32	0	17	0	0
T33	0	49	0	0
T34	0	25	0	0
T35	0	5	0	0
T36	0	19	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1882	0	0
T11	603682	39	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	30	0	0
T29	0	30	0	0
T30	0	17	0	0
T31	0	16	0	0
T32	0	16	0	0
T33	0	39	0	0
T34	0	14	0	0
T35	0	4	0	0
T36	0	13	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2031	0	0
T11	603682	34	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	19	0	0
T29	0	25	0	0
T30	0	14	0	0
T31	0	5	0	0
T32	0	11	0	0
T33	0	22	0	0
T34	0	19	0	0
T35	0	4	0	0
T36	0	27	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2023	0	0
T11	603682	28	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	21	0	0
T29	0	58	0	0
T30	0	12	0	0
T31	0	22	0	0
T32	0	23	0	0
T33	0	23	0	0
T34	0	22	0	0
T36	0	13	0	0
T37	0	49	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T11	603682	39	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	19	0	0
T29	0	46	0	0
T30	0	7	0	0
T31	0	22	0	0
T32	0	15	0	0
T33	0	37	0	0
T34	0	16	0	0
T36	0	21	0	0
T37	0	39	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2046	0	0
T11	603682	25	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	17	0	0
T29	0	25	0	0
T30	0	25	0	0
T31	0	27	0	0
T32	0	25	0	0
T33	0	33	0	0
T34	0	15	0	0
T35	0	19	0	0
T36	0	15	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1726	0	0
T11	603682	53	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	16	0	0
T29	0	43	0	0
T30	0	12	0	0
T31	0	16	0	0
T32	0	23	0	0
T33	0	26	0	0
T34	0	37	0	0
T35	0	6	0	0
T36	0	7	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653	0	0
T11	603682	35	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	28	0	0
T29	0	42	0	0
T30	0	10	0	0
T31	0	25	0	0
T32	0	17	0	0
T33	0	33	0	0
T34	0	23	0	0
T35	0	14	0	0
T36	0	15	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1960	0	0
T11	603682	35	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	16	0	0
T29	0	30	0	0
T30	0	10	0	0
T31	0	18	0	0
T32	0	18	0	0
T33	0	40	0	0
T34	0	28	0	0
T35	0	8	0	0
T36	0	21	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1735	0	0
T11	603682	53	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	28	0	0
T29	0	38	0	0
T30	0	17	0	0
T31	0	15	0	0
T32	0	29	0	0
T33	0	22	0	0
T34	0	11	0	0
T35	0	21	0	0
T36	0	21	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1837	0	0
T11	603682	41	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	21	0	0
T29	0	36	0	0
T30	0	19	0	0
T31	0	18	0	0
T32	0	11	0	0
T33	0	39	0	0
T34	0	20	0	0
T35	0	3	0	0
T36	0	19	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1662	0	0
T11	603682	43	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	19	0	0
T29	0	16	0	0
T30	0	19	0	0
T31	0	16	0	0
T32	0	9	0	0
T33	0	54	0	0
T34	0	25	0	0
T35	0	21	0	0
T36	0	18	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1653	0	0
T11	603682	27	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	14	0	0
T29	0	34	0	0
T30	0	11	0	0
T31	0	19	0	0
T32	0	15	0	0
T33	0	43	0	0
T34	0	9	0	0
T35	0	2	0	0
T36	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1893	0	0
T11	603682	48	0	0
T12	218095	0	0	0
T13	197407	0	0	0
T14	419195	0	0	0
T15	165631	0	0	0
T23	470554	0	0	0
T24	101986	0	0	0
T25	113057	0	0	0
T26	43150	0	0	0
T27	139711	0	0	0
T28	0	25	0	0
T29	0	51	0	0
T30	0	15	0	0
T31	0	10	0	0
T32	0	29	0	0
T33	0	66	0	0
T34	0	18	0	0
T38	0	10	0	0
T39	0	17	0	0