Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5357	1			T1	20		T4	6		T5	20
testmodes[AdcCtrlTestmodeNormal]	4670	1			T4	9		T7	8		T8	2
testmodes[AdcCtrlTestmodeLowpower]	4876	1			T8	1		T9	14		T12	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2693	1			T1	19		T4	2		T5	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1416	1			T4	3		T7	4		T10	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1133	1			T13	1		T128	1		T31	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1406	1			T4	3		T7	4		T10	6
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1714	1			T4	6		T7	4		T10	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1231	1			T8	1		T14	1		T15	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1143	1			T13	1		T128	1		T53	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1206	1			T8	1		T14	1		T15	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2278	1			T9	13		T12	10		T15	3