Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.07 96.67 100.00 100.00 98.82 98.33 90.79


Total tests in report: 901
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
71.27 71.27 96.93 96.93 79.58 79.58 87.44 87.44 40.54 40.54 95.03 95.03 88.81 88.81 10.56 10.56 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.323585182
77.26 5.99 97.99 1.05 91.31 11.73 95.50 8.06 45.95 5.41 97.14 2.11 93.49 4.67 19.47 8.91 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2874480763
80.71 3.45 98.54 0.56 92.84 1.52 96.68 1.18 62.16 16.22 98.14 0.99 94.49 1.00 22.14 2.67 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.225466109
83.97 3.26 98.54 0.00 92.88 0.04 96.68 0.00 83.78 21.62 98.20 0.06 94.49 0.00 23.23 1.10 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3668173584
86.21 2.24 98.64 0.09 93.78 0.91 96.68 0.00 89.19 5.41 98.32 0.12 95.99 1.50 30.87 7.64 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.2013220405
87.88 1.67 98.76 0.12 94.03 0.25 97.16 0.47 97.30 8.11 98.39 0.06 95.99 0.00 33.52 2.65 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3782461403
89.08 1.20 98.76 0.00 94.11 0.08 97.16 0.00 97.30 0.00 98.39 0.00 95.99 0.00 41.85 8.34 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1645274117
89.93 0.85 98.76 0.00 94.11 0.00 97.16 0.00 97.30 0.00 98.39 0.00 95.99 0.00 47.82 5.96 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3099284340
90.69 0.76 98.76 0.00 94.11 0.00 97.16 0.00 97.30 0.00 98.39 0.00 95.99 0.00 53.11 5.29 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1690058942
91.40 0.71 98.88 0.12 94.24 0.12 97.16 0.00 97.30 0.00 98.57 0.19 95.99 0.00 57.65 4.54 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.1869932459
91.95 0.55 98.88 0.00 94.24 0.00 97.16 0.00 100.00 2.70 98.57 0.00 95.99 0.00 58.82 1.17 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all.885841714
92.48 0.53 98.88 0.00 94.24 0.00 97.16 0.00 100.00 0.00 98.57 0.00 95.99 0.00 62.54 3.72 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.382860172
92.94 0.45 98.88 0.00 94.24 0.00 97.16 0.00 100.00 0.00 98.57 0.00 95.99 0.00 65.71 3.17 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3035605895
93.36 0.42 98.88 0.00 95.51 1.28 97.63 0.47 100.00 0.00 98.63 0.06 96.49 0.50 66.36 0.65 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2488882080
93.76 0.40 98.92 0.03 95.64 0.12 99.76 2.13 100.00 0.00 98.70 0.06 96.83 0.33 66.48 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3541095066
94.13 0.37 98.92 0.00 95.68 0.04 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.17 68.85 2.37 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.829503654
94.45 0.32 98.92 0.00 95.68 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 71.10 2.25 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4062766844
94.72 0.27 98.92 0.00 95.68 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 73.02 1.92 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3704139481
95.00 0.27 98.92 0.00 95.68 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 74.94 1.92 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_wakeup.3611573015
95.24 0.24 98.92 0.00 95.68 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 76.64 1.70 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.153238302
95.45 0.21 98.92 0.00 95.68 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 78.11 1.47 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2867821058
95.63 0.18 98.98 0.06 95.92 0.25 99.76 0.00 100.00 0.00 98.82 0.12 97.83 0.83 78.11 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2292872747
95.81 0.18 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 79.36 1.25 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2747001903
95.95 0.14 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 80.31 0.95 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2473843955
96.08 0.13 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 81.23 0.92 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_both.3454649487
96.20 0.12 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 82.08 0.85 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_clock_gating.1633957018
96.31 0.11 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 82.83 0.75 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2089810370
96.40 0.09 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 83.48 0.65 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2791694049
96.49 0.09 98.98 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 84.10 0.62 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.2876573338
96.56 0.07 98.98 0.00 96.25 0.33 99.76 0.00 100.00 0.00 98.82 0.00 97.83 0.00 84.28 0.17 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2323205515
96.63 0.07 98.98 0.00 96.25 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.33 0.50 84.28 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3125877030
96.70 0.07 98.98 0.00 96.25 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.33 0.00 84.78 0.50 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3269800782
96.77 0.07 98.98 0.00 96.25 0.00 99.76 0.00 100.00 0.00 98.82 0.00 98.33 0.00 85.25 0.47 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_both.3426346093
96.84 0.06 99.07 0.09 96.38 0.12 100.00 0.24 100.00 0.00 98.82 0.00 98.33 0.00 85.25 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.765451882
96.90 0.06 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 85.70 0.45 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3686412384
96.96 0.06 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.12 0.42 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1937283040
97.01 0.05 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.45 0.32 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3572196378
97.05 0.04 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 86.75 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_interrupt.627921697
97.09 0.04 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.05 0.30 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1662671531
97.13 0.04 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.32 0.27 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_clock_gating.3812596318
97.17 0.04 99.07 0.00 96.38 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.57 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.81668966
97.20 0.03 99.07 0.00 96.58 0.21 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.60 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1490682034
97.23 0.03 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 87.82 0.22 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.4208735592
97.26 0.03 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.02 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1688872113
97.29 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.20 0.17 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1933046821
97.31 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.35 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all.1238080425
97.33 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.50 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/45.adc_ctrl_clock_gating.2214846540
97.35 0.02 99.07 0.00 96.58 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.64 0.15 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/46.adc_ctrl_filters_both.2195607542
97.37 0.02 99.07 0.00 96.67 0.08 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.69 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3881536743
97.39 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.82 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/22.adc_ctrl_filters_wakeup.377548151
97.40 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 88.94 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/28.adc_ctrl_stress_all.2396894116
97.42 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.07 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/34.adc_ctrl_filters_interrupt.2005705799
97.44 0.02 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.19 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_clock_gating.1836198113
97.45 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.29 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_both.489068393
97.47 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.39 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.4137223314
97.48 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.49 0.10 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.2267587707
97.49 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.57 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3704523763
97.50 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.64 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3341960196
97.51 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.72 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.9487266
97.53 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.79 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/36.adc_ctrl_filters_wakeup.805145120
97.54 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.87 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1127679522
97.55 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.94 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3673093350
97.55 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 89.99 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2604854890
97.56 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.04 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.4113450369
97.57 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.09 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_fsm_reset.301921262
97.58 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.14 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.1785824622
97.58 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.19 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_filters_polled.605498692
97.59 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.24 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.164611021
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.29 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_fsm_reset.52932230
97.60 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.34 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/30.adc_ctrl_filters_polled.3075098919
97.61 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.39 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_fsm_reset.1522755424
97.62 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.44 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_clock_gating.168208193
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.49 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_polled.2560129125
97.63 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.54 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2866827598
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.57 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2225347760
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.59 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.52786936
97.64 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.62 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2676156359
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.64 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_wakeup.3414184639
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.67 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.889888576
97.65 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.69 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_clock_gating.3522847271
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.72 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_fsm_reset.3388714811
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.74 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.3077266629
97.66 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.77 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_clock_gating.1672858032
97.67 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.82 0.00 98.33 0.00 90.79 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_wakeup.1311612959

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.586304974
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1891835158
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3520338111
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.119444422
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1716300678
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.2184467285
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3766877103
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1924290586
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.6739164
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.210725421
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1864719553
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.639363487
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.2255391447
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3492243839
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2920722221
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2101495465
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1946285199
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3077093231
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2481854290
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2174385759
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3857576363
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.631258374
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3765503443
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3978639276
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3922546693
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2683351156
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2175186632
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.30592847
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2582942133
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.3976141042
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4148634870
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2939805891
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1151220579
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1744931095
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.770539387
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.1994007379
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3845078050
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2348158309
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.892233638
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2302990322
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2358763549
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.2668593830
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3586244714
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.786369765
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1347999668
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.781596811
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.346861112
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3119207006
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.869023003
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3684148777
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.877936333
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.281887324
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.907688771
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.2438166262
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.765527541
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.940608450
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1579237536
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3333136029
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3129094434
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.714467898
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.928881091
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1656747643
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2248869452
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3596691834
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2845585027
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.1482658414
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2249531494
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1753461189
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.189359853
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1729060278
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2292319343
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.3894545874
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3420301612
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2054832678
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3520176913
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1713650528
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.901484714
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2474631873
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4128375769
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.1303435360
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2397367936
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3156232798
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4258312711
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.2065145402
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.1268929749
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.3974742615
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.3484061248
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.913972132
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.1325621538
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.205117815
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2342303138
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2288735602
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.1002861711
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1109378026
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1399962210
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3541173752
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3285067516
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1556460405
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.2541608467
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1172337896
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1150465972
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.4216917477
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.2376746464
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.2123944782
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.3559265430
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.941176529
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.2291770443
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2044447128
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.817957023
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.2814643930
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.2988634545
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.793338067
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1560087677
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.281310774
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.469583525
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.824657739
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.4237810024
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.989362185
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.680464142
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2236448177
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_alert_test.14655789
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.3278764929
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_filters_both.3060902832
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3931632528
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3156592298
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3334513252
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.163421716
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2133187409
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.30785426
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1451768119
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3299594198
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.492595291
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3988062229
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.839767420
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.2645951349
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2051134755
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2607287133
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1591323785
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2441388122
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/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3052568929
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.2932321870
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2534358823
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.331354669
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3490940881
/workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.951885196



Total test records in report: 901
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1814360061 Oct 09 06:06:57 AM UTC 24 Oct 09 06:07:05 AM UTC 24 5781376976 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.3541095066 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:30 AM UTC 24 8128568706 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.3320712364 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:30 AM UTC 24 378545129 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.765451882 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:32 AM UTC 24 443266202 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1989348194 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:34 AM UTC 24 4164265031 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.2317740491 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:35 AM UTC 24 5786692447 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.2953367102 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:35 AM UTC 24 6012958425 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.2506356311 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:36 AM UTC 24 7666345817 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.225466109 Oct 09 06:07:16 AM UTC 24 Oct 09 06:07:37 AM UTC 24 3618682795 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.323585182 Oct 09 06:07:31 AM UTC 24 Oct 09 06:07:39 AM UTC 24 4129621966 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.1906701804 Oct 09 06:07:17 AM UTC 24 Oct 09 06:07:42 AM UTC 24 33442397442 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.2879004327 Oct 09 06:07:39 AM UTC 24 Oct 09 06:07:44 AM UTC 24 4822651983 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1258735090 Oct 09 06:07:44 AM UTC 24 Oct 09 06:07:46 AM UTC 24 457992731 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2941377423 Oct 09 06:07:33 AM UTC 24 Oct 09 06:07:46 AM UTC 24 507222204 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.1680596339 Oct 09 06:07:07 AM UTC 24 Oct 09 06:07:49 AM UTC 24 8896789548 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.2578328218 Oct 09 06:07:04 AM UTC 24 Oct 09 06:07:52 AM UTC 24 24252940136 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.2960901222 Oct 09 06:07:43 AM UTC 24 Oct 09 06:07:54 AM UTC 24 7908524021 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.1809276868 Oct 09 06:07:48 AM UTC 24 Oct 09 06:07:55 AM UTC 24 4072183996 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.1889149400 Oct 09 06:07:31 AM UTC 24 Oct 09 06:07:55 AM UTC 24 7781361000 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2679766749 Oct 09 06:07:35 AM UTC 24 Oct 09 06:07:56 AM UTC 24 5808467679 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.93986340 Oct 09 06:07:54 AM UTC 24 Oct 09 06:07:57 AM UTC 24 521992556 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.816825813 Oct 09 06:07:44 AM UTC 24 Oct 09 06:07:58 AM UTC 24 5841738131 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1490682034 Oct 09 06:07:50 AM UTC 24 Oct 09 06:08:02 AM UTC 24 5392983962 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3971746523 Oct 09 06:07:07 AM UTC 24 Oct 09 06:08:09 AM UTC 24 72702594717 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3782461403 Oct 09 06:07:43 AM UTC 24 Oct 09 06:08:09 AM UTC 24 11505387046 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2117645282 Oct 09 06:07:56 AM UTC 24 Oct 09 06:08:21 AM UTC 24 5696797313 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.671828094 Oct 09 06:06:57 AM UTC 24 Oct 09 06:08:29 AM UTC 24 168450180800 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.3878090519 Oct 09 06:08:23 AM UTC 24 Oct 09 06:08:30 AM UTC 24 3482620440 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.3374718778 Oct 09 06:07:41 AM UTC 24 Oct 09 06:08:35 AM UTC 24 34532300991 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.2981930729 Oct 09 06:06:57 AM UTC 24 Oct 09 06:08:45 AM UTC 24 164860100451 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.1565379646 Oct 09 06:07:07 AM UTC 24 Oct 09 06:08:46 AM UTC 24 162243374857 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.3931632528 Oct 09 06:08:48 AM UTC 24 Oct 09 06:08:50 AM UTC 24 474602862 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3811831155 Oct 09 06:07:46 AM UTC 24 Oct 09 06:08:51 AM UTC 24 162905790906 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.2874480763 Oct 09 06:07:36 AM UTC 24 Oct 09 06:08:53 AM UTC 24 499151466131 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.614795305 Oct 09 06:07:48 AM UTC 24 Oct 09 06:08:57 AM UTC 24 38129975435 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.2765775828 Oct 09 06:07:46 AM UTC 24 Oct 09 06:08:58 AM UTC 24 164243318571 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.285708294 Oct 09 06:08:37 AM UTC 24 Oct 09 06:08:59 AM UTC 24 16129514669 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.1676349409 Oct 09 06:08:51 AM UTC 24 Oct 09 06:09:00 AM UTC 24 5747038996 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.1933046821 Oct 09 06:07:07 AM UTC 24 Oct 09 06:09:42 AM UTC 24 339441729816 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2867379121 Oct 09 06:07:07 AM UTC 24 Oct 09 06:09:47 AM UTC 24 42856832903 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.2645951349 Oct 09 06:09:47 AM UTC 24 Oct 09 06:09:52 AM UTC 24 3084142032 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.1166551416 Oct 09 06:07:44 AM UTC 24 Oct 09 06:09:52 AM UTC 24 161122973998 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.2013220405 Oct 09 06:07:04 AM UTC 24 Oct 09 06:09:55 AM UTC 24 520411027992 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.3016202628 Oct 09 06:08:31 AM UTC 24 Oct 09 06:10:10 AM UTC 24 25739515643 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.427188498 Oct 09 06:10:11 AM UTC 24 Oct 09 06:10:14 AM UTC 24 406311764 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1632652972 Oct 09 06:09:53 AM UTC 24 Oct 09 06:10:15 AM UTC 24 2064332514 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3704139481 Oct 09 06:07:04 AM UTC 24 Oct 09 06:10:16 AM UTC 24 203052171453 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.163421716 Oct 09 06:07:56 AM UTC 24 Oct 09 06:10:16 AM UTC 24 160880753443 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.3475171363 Oct 09 06:09:48 AM UTC 24 Oct 09 06:10:19 AM UTC 24 26127462077 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3334513252 Oct 09 06:07:59 AM UTC 24 Oct 09 06:10:21 AM UTC 24 163434295339 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3988062229 Oct 09 06:08:59 AM UTC 24 Oct 09 06:10:23 AM UTC 24 186891926587 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.1026160304 Oct 09 06:07:31 AM UTC 24 Oct 09 06:10:25 AM UTC 24 236209144679 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3318754348 Oct 09 06:07:46 AM UTC 24 Oct 09 06:10:25 AM UTC 24 196494132990 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.829503654 Oct 09 06:08:11 AM UTC 24 Oct 09 06:10:28 AM UTC 24 521503045311 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.3440843601 Oct 09 06:10:15 AM UTC 24 Oct 09 06:10:42 AM UTC 24 5948534443 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.120157174 Oct 09 06:10:29 AM UTC 24 Oct 09 06:10:44 AM UTC 24 3379550079 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.2658701026 Oct 09 06:07:59 AM UTC 24 Oct 09 06:10:48 AM UTC 24 527307611215 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.3243447619 Oct 09 06:07:36 AM UTC 24 Oct 09 06:10:54 AM UTC 24 332265293959 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.857389113 Oct 09 06:07:07 AM UTC 24 Oct 09 06:11:04 AM UTC 24 317184285136 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1662671531 Oct 09 06:10:49 AM UTC 24 Oct 09 06:11:08 AM UTC 24 10949203983 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.3821450568 Oct 09 06:11:05 AM UTC 24 Oct 09 06:11:08 AM UTC 24 466465140 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.331354669 Oct 09 06:11:08 AM UTC 24 Oct 09 06:11:26 AM UTC 24 5766389524 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.607379145 Oct 09 06:07:46 AM UTC 24 Oct 09 06:11:43 AM UTC 24 337133149597 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.3596857248 Oct 09 06:06:57 AM UTC 24 Oct 09 06:11:52 AM UTC 24 488312030273 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.2051134755 Oct 09 06:10:16 AM UTC 24 Oct 09 06:11:57 AM UTC 24 168560943496 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.571978785 Oct 09 06:10:43 AM UTC 24 Oct 09 06:12:01 AM UTC 24 38134947732 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.3269800782 Oct 09 06:07:07 AM UTC 24 Oct 09 06:12:05 AM UTC 24 342766100364 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4245938229 Oct 09 06:08:03 AM UTC 24 Oct 09 06:12:06 AM UTC 24 624747322385 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.492595291 Oct 09 06:08:52 AM UTC 24 Oct 09 06:12:07 AM UTC 24 163006401058 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.2534358823 Oct 09 06:12:08 AM UTC 24 Oct 09 06:12:25 AM UTC 24 3802712333 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.447692584 Oct 09 06:07:36 AM UTC 24 Oct 09 06:12:26 AM UTC 24 163510178578 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3035605895 Oct 09 06:07:37 AM UTC 24 Oct 09 06:12:37 AM UTC 24 555879747980 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.337449792 Oct 09 06:07:37 AM UTC 24 Oct 09 06:12:43 AM UTC 24 186397134616 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2693758068 Oct 09 06:06:57 AM UTC 24 Oct 09 06:12:48 AM UTC 24 614193341334 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.951885196 Oct 09 06:12:37 AM UTC 24 Oct 09 06:12:50 AM UTC 24 111017056846 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.2169660024 Oct 09 06:12:49 AM UTC 24 Oct 09 06:12:52 AM UTC 24 298014781 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.2747001903 Oct 09 06:07:07 AM UTC 24 Oct 09 06:12:53 AM UTC 24 497478120993 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.2532345110 Oct 09 06:12:51 AM UTC 24 Oct 09 06:13:02 AM UTC 24 6137914847 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.3490940881 Oct 09 06:12:44 AM UTC 24 Oct 09 06:13:06 AM UTC 24 25568612670 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1451768119 Oct 09 06:08:53 AM UTC 24 Oct 09 06:13:22 AM UTC 24 322997665698 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_stress_all.242789579 Oct 09 06:09:55 AM UTC 24 Oct 09 06:13:53 AM UTC 24 68645417710 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1231410220 Oct 09 06:07:07 AM UTC 24 Oct 09 06:13:54 AM UTC 24 630889869439 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.3522250982 Oct 09 06:07:36 AM UTC 24 Oct 09 06:14:01 AM UTC 24 160430143225 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.1645274117 Oct 09 06:07:16 AM UTC 24 Oct 09 06:14:11 AM UTC 24 574170122624 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.3673093350 Oct 09 06:08:58 AM UTC 24 Oct 09 06:14:16 AM UTC 24 352781659935 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1038053983 Oct 09 06:14:11 AM UTC 24 Oct 09 06:14:23 AM UTC 24 4614782028 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1974705166 Oct 09 06:07:07 AM UTC 24 Oct 09 06:14:44 AM UTC 24 603014378411 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1688872113 Oct 09 06:07:30 AM UTC 24 Oct 09 06:14:48 AM UTC 24 101896013714 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.3436853166 Oct 09 06:07:07 AM UTC 24 Oct 09 06:14:53 AM UTC 24 117245162314 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2517895276 Oct 09 06:14:45 AM UTC 24 Oct 09 06:14:54 AM UTC 24 4955868094 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.777729225 Oct 09 06:14:54 AM UTC 24 Oct 09 06:14:56 AM UTC 24 413441890 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2225347760 Oct 09 06:13:55 AM UTC 24 Oct 09 06:15:04 AM UTC 24 175153818093 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2916559158 Oct 09 06:07:07 AM UTC 24 Oct 09 06:15:09 AM UTC 24 332255059496 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.306752940 Oct 09 06:14:18 AM UTC 24 Oct 09 06:15:17 AM UTC 24 35795822108 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.4223823549 Oct 09 06:14:54 AM UTC 24 Oct 09 06:15:19 AM UTC 24 5903219348 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.355107774 Oct 09 06:10:20 AM UTC 24 Oct 09 06:15:22 AM UTC 24 332847768228 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled_fixed.517700059 Oct 09 06:07:44 AM UTC 24 Oct 09 06:15:30 AM UTC 24 161847957619 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.3790838079 Oct 09 06:10:15 AM UTC 24 Oct 09 06:15:37 AM UTC 24 493954753749 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.2932321870 Oct 09 06:12:26 AM UTC 24 Oct 09 06:15:45 AM UTC 24 46720524998 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1505736875 Oct 09 06:15:46 AM UTC 24 Oct 09 06:16:04 AM UTC 24 4993231804 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3447665380 Oct 09 06:14:49 AM UTC 24 Oct 09 06:16:16 AM UTC 24 336477381983 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.3226914786 Oct 09 06:11:27 AM UTC 24 Oct 09 06:16:21 AM UTC 24 336367460581 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2276029456 Oct 09 06:07:46 AM UTC 24 Oct 09 06:16:23 AM UTC 24 168418145763 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.1713467740 Oct 09 06:09:01 AM UTC 24 Oct 09 06:16:29 AM UTC 24 160350643606 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.1209387492 Oct 09 06:16:30 AM UTC 24 Oct 09 06:16:33 AM UTC 24 496546718 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1883972090 Oct 09 06:10:23 AM UTC 24 Oct 09 06:16:39 AM UTC 24 396263492690 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.3107316412 Oct 09 06:10:21 AM UTC 24 Oct 09 06:16:48 AM UTC 24 340849791522 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.2604854890 Oct 09 06:14:57 AM UTC 24 Oct 09 06:16:51 AM UTC 24 165392183969 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1591323785 Oct 09 06:11:09 AM UTC 24 Oct 09 06:16:51 AM UTC 24 490683728256 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.1878215480 Oct 09 06:16:34 AM UTC 24 Oct 09 06:16:57 AM UTC 24 5664164592 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.839767420 Oct 09 06:09:53 AM UTC 24 Oct 09 06:17:17 AM UTC 24 80956006946 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2676156359 Oct 09 06:16:21 AM UTC 24 Oct 09 06:17:22 AM UTC 24 364409092927 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.839711228 Oct 09 06:12:06 AM UTC 24 Oct 09 06:17:26 AM UTC 24 355662656725 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.1127679522 Oct 09 06:07:46 AM UTC 24 Oct 09 06:17:28 AM UTC 24 445395833121 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3223071351 Oct 09 06:11:53 AM UTC 24 Oct 09 06:17:31 AM UTC 24 484549608275 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1421508249 Oct 09 06:17:26 AM UTC 24 Oct 09 06:17:34 AM UTC 24 4843984294 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.3768962390 Oct 09 06:16:05 AM UTC 24 Oct 09 06:18:00 AM UTC 24 31432133274 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3806218254 Oct 09 06:07:43 AM UTC 24 Oct 09 06:18:02 AM UTC 24 94691217626 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.409420322 Oct 09 06:18:03 AM UTC 24 Oct 09 06:18:05 AM UTC 24 403898416 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2145807965 Oct 09 06:17:34 AM UTC 24 Oct 09 06:18:09 AM UTC 24 5595182071 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.2013358791 Oct 09 06:17:28 AM UTC 24 Oct 09 06:18:09 AM UTC 24 34700028509 ps
T373 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.1082524779 Oct 09 06:18:06 AM UTC 24 Oct 09 06:18:10 AM UTC 24 5669766213 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all.3668173584 Oct 09 06:07:43 AM UTC 24 Oct 09 06:18:14 AM UTC 24 111539537560 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.2133187409 Oct 09 06:08:31 AM UTC 24 Oct 09 06:18:28 AM UTC 24 118551341199 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1744737157 Oct 09 06:13:03 AM UTC 24 Oct 09 06:18:33 AM UTC 24 162266814798 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3341960196 Oct 09 06:15:20 AM UTC 24 Oct 09 06:19:09 AM UTC 24 345505792772 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1690058942 Oct 09 06:15:31 AM UTC 24 Oct 09 06:19:14 AM UTC 24 512895752510 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.2280608891 Oct 09 06:10:26 AM UTC 24 Oct 09 06:19:19 AM UTC 24 169412557714 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1211829806 Oct 09 06:16:52 AM UTC 24 Oct 09 06:19:21 AM UTC 24 167411093159 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.3670700224 Oct 09 06:10:16 AM UTC 24 Oct 09 06:19:23 AM UTC 24 165181205438 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.2473843955 Oct 09 06:14:02 AM UTC 24 Oct 09 06:19:27 AM UTC 24 356935852627 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.30785426 Oct 09 06:09:42 AM UTC 24 Oct 09 06:19:31 AM UTC 24 330837619534 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1937283040 Oct 09 06:15:18 AM UTC 24 Oct 09 06:19:34 AM UTC 24 327942543358 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.3468435375 Oct 09 06:19:35 AM UTC 24 Oct 09 06:19:38 AM UTC 24 302650197 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1843039673 Oct 09 06:19:28 AM UTC 24 Oct 09 06:19:41 AM UTC 24 14059286804 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.4062766844 Oct 09 06:07:37 AM UTC 24 Oct 09 06:19:42 AM UTC 24 337845967453 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.3251705532 Oct 09 06:19:20 AM UTC 24 Oct 09 06:19:43 AM UTC 24 5163941281 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.424633437 Oct 09 06:19:39 AM UTC 24 Oct 09 06:20:01 AM UTC 24 6082972871 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.2358343363 Oct 09 06:08:52 AM UTC 24 Oct 09 06:20:07 AM UTC 24 327946409285 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.961012907 Oct 09 06:07:07 AM UTC 24 Oct 09 06:20:12 AM UTC 24 320288066476 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2010488435 Oct 09 06:10:45 AM UTC 24 Oct 09 06:20:18 AM UTC 24 118508782732 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all.3099284340 Oct 09 06:07:06 AM UTC 24 Oct 09 06:20:19 AM UTC 24 609404205782 ps
T381 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.2476451904 Oct 09 06:19:22 AM UTC 24 Oct 09 06:20:37 AM UTC 24 29051088038 ps
T382 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.948827051 Oct 09 06:18:15 AM UTC 24 Oct 09 06:20:39 AM UTC 24 161818916734 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3808556652 Oct 09 06:14:24 AM UTC 24 Oct 09 06:20:50 AM UTC 24 104518557116 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.1878901905 Oct 09 06:20:38 AM UTC 24 Oct 09 06:20:54 AM UTC 24 3498492167 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.2607287133 Oct 09 06:11:45 AM UTC 24 Oct 09 06:20:56 AM UTC 24 165272195055 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.1069120932 Oct 09 06:07:54 AM UTC 24 Oct 09 06:21:14 AM UTC 24 131377495368 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2563085729 Oct 09 06:07:07 AM UTC 24 Oct 09 06:21:15 AM UTC 24 331352031825 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2809179065 Oct 09 06:15:38 AM UTC 24 Oct 09 06:21:17 AM UTC 24 164669481045 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.388032182 Oct 09 06:21:15 AM UTC 24 Oct 09 06:21:19 AM UTC 24 504259251 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.300892582 Oct 09 06:20:54 AM UTC 24 Oct 09 06:21:21 AM UTC 24 8477269587 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.1869932459 Oct 09 06:17:18 AM UTC 24 Oct 09 06:21:23 AM UTC 24 627308492239 ps
T386 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.2006976568 Oct 09 06:21:16 AM UTC 24 Oct 09 06:21:25 AM UTC 24 5855993018 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.1247823965 Oct 09 06:17:23 AM UTC 24 Oct 09 06:21:32 AM UTC 24 208360337235 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup.3374256231 Oct 09 06:16:58 AM UTC 24 Oct 09 06:21:33 AM UTC 24 348557920732 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.2866827598 Oct 09 06:07:50 AM UTC 24 Oct 09 06:21:46 AM UTC 24 115401653848 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.2272528827 Oct 09 06:07:04 AM UTC 24 Oct 09 06:21:51 AM UTC 24 329567361159 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2670161153 Oct 09 06:16:52 AM UTC 24 Oct 09 06:21:53 AM UTC 24 327461823285 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.4272316775 Oct 09 06:21:17 AM UTC 24 Oct 09 06:21:54 AM UTC 24 166632772519 ps
T388 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1707080861 Oct 09 06:20:02 AM UTC 24 Oct 09 06:21:56 AM UTC 24 163838725769 ps
T389 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.280482924 Oct 09 06:21:51 AM UTC 24 Oct 09 06:21:58 AM UTC 24 5104183180 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3250869645 Oct 09 06:20:40 AM UTC 24 Oct 09 06:22:10 AM UTC 24 23579644779 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3630302241 Oct 09 06:21:56 AM UTC 24 Oct 09 06:22:11 AM UTC 24 7878805236 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.768164314 Oct 09 06:22:11 AM UTC 24 Oct 09 06:22:13 AM UTC 24 449163009 ps
T392 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.3124159568 Oct 09 06:22:12 AM UTC 24 Oct 09 06:22:16 AM UTC 24 6017701215 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1432447742 Oct 09 06:20:20 AM UTC 24 Oct 09 06:22:22 AM UTC 24 174735534641 ps
T393 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.11769466 Oct 09 06:15:22 AM UTC 24 Oct 09 06:22:25 AM UTC 24 395597712148 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all.2244001253 Oct 09 06:20:56 AM UTC 24 Oct 09 06:22:29 AM UTC 24 30577092418 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all.2322940923 Oct 09 06:21:58 AM UTC 24 Oct 09 06:22:38 AM UTC 24 38459509583 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.3404667669 Oct 09 06:10:55 AM UTC 24 Oct 09 06:22:55 AM UTC 24 254903752139 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.2791694049 Oct 09 06:19:15 AM UTC 24 Oct 09 06:22:59 AM UTC 24 375399000535 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3044810452 Oct 09 06:18:00 AM UTC 24 Oct 09 06:23:06 AM UTC 24 330424213678 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.3795778682 Oct 09 06:18:11 AM UTC 24 Oct 09 06:23:06 AM UTC 24 332050441500 ps
T396 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.2226310453 Oct 09 06:23:06 AM UTC 24 Oct 09 06:23:18 AM UTC 24 4274373530 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1389731947 Oct 09 06:16:48 AM UTC 24 Oct 09 06:23:19 AM UTC 24 324598626338 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.2849929884 Oct 09 06:23:06 AM UTC 24 Oct 09 06:23:31 AM UTC 24 46308917727 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3768053794 Oct 09 06:12:53 AM UTC 24 Oct 09 06:23:31 AM UTC 24 483100691604 ps
T399 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.3152453119 Oct 09 06:21:53 AM UTC 24 Oct 09 06:23:35 AM UTC 24 29943263843 ps
T400 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.1125895942 Oct 09 06:23:33 AM UTC 24 Oct 09 06:23:35 AM UTC 24 427316824 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2052833898 Oct 09 06:23:20 AM UTC 24 Oct 09 06:23:35 AM UTC 24 1546274324 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_polled_fixed.4169184041 Oct 09 06:19:42 AM UTC 24 Oct 09 06:23:38 AM UTC 24 487980040978 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.1549710694 Oct 09 06:23:35 AM UTC 24 Oct 09 06:23:42 AM UTC 24 5698494620 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.4113450369 Oct 09 06:20:19 AM UTC 24 Oct 09 06:23:44 AM UTC 24 368985848404 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2089810370 Oct 09 06:08:11 AM UTC 24 Oct 09 06:23:45 AM UTC 24 344550657710 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.3628907135 Oct 09 06:21:34 AM UTC 24 Oct 09 06:23:48 AM UTC 24 193205088202 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.3496449213 Oct 09 06:08:48 AM UTC 24 Oct 09 06:23:53 AM UTC 24 280248547606 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.52786936 Oct 09 06:16:23 AM UTC 24 Oct 09 06:23:53 AM UTC 24 324976427741 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.2441388122 Oct 09 06:11:58 AM UTC 24 Oct 09 06:23:56 AM UTC 24 537385268583 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.180602118 Oct 09 06:23:55 AM UTC 24 Oct 09 06:24:00 AM UTC 24 3843183732 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3212782949 Oct 09 06:07:04 AM UTC 24 Oct 09 06:24:04 AM UTC 24 353546589781 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled_fixed.1720666799 Oct 09 06:15:05 AM UTC 24 Oct 09 06:24:14 AM UTC 24 483052044512 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.1436154807 Oct 09 06:16:17 AM UTC 24 Oct 09 06:24:19 AM UTC 24 97764047672 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4150225258 Oct 09 06:24:05 AM UTC 24 Oct 09 06:24:20 AM UTC 24 5971559528 ps
T405 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3300376535 Oct 09 06:22:39 AM UTC 24 Oct 09 06:24:20 AM UTC 24 194262616463 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.2325397900 Oct 09 06:07:07 AM UTC 24 Oct 09 06:24:22 AM UTC 24 336228053304 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3774033480 Oct 09 06:24:20 AM UTC 24 Oct 09 06:24:24 AM UTC 24 345264779 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup.3049129484 Oct 09 06:21:26 AM UTC 24 Oct 09 06:24:27 AM UTC 24 189018963092 ps
T407 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.319284984 Oct 09 06:24:21 AM UTC 24 Oct 09 06:24:50 AM UTC 24 6064877498 ps
T408 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.2736802238 Oct 09 06:22:17 AM UTC 24 Oct 09 06:25:04 AM UTC 24 321220379917 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2867821058 Oct 09 06:21:47 AM UTC 24 Oct 09 06:25:11 AM UTC 24 497291525038 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.382860172 Oct 09 06:12:07 AM UTC 24 Oct 09 06:25:28 AM UTC 24 514416250442 ps
T409 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3899134802 Oct 09 06:20:14 AM UTC 24 Oct 09 06:25:32 AM UTC 24 195652307595 ps
T410 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.556336360 Oct 09 06:25:33 AM UTC 24 Oct 09 06:25:37 AM UTC 24 3827079938 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2335495784 Oct 09 06:20:50 AM UTC 24 Oct 09 06:26:00 AM UTC 24 78080758350 ps
T412 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1440992399 Oct 09 06:25:38 AM UTC 24 Oct 09 06:26:05 AM UTC 24 26056463420 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_clock_gating.3464084402 Oct 09 06:23:48 AM UTC 24 Oct 09 06:26:06 AM UTC 24 165559926743 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.7061181 Oct 09 06:26:06 AM UTC 24 Oct 09 06:26:18 AM UTC 24 16867003063 ps
T413 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2369279015 Oct 09 06:21:33 AM UTC 24 Oct 09 06:26:18 AM UTC 24 197191392966 ps
T414 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.4119695077 Oct 09 06:23:57 AM UTC 24 Oct 09 06:26:19 AM UTC 24 34612858476 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3506603935 Oct 09 06:26:18 AM UTC 24 Oct 09 06:26:21 AM UTC 24 435350191 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.3156592298 Oct 09 06:07:59 AM UTC 24 Oct 09 06:26:22 AM UTC 24 338371428937 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.595841076 Oct 09 06:21:20 AM UTC 24 Oct 09 06:26:26 AM UTC 24 505959880995 ps
T417 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1571858857 Oct 09 06:21:24 AM UTC 24 Oct 09 06:26:27 AM UTC 24 330317595432 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.3572196378 Oct 09 06:06:57 AM UTC 24 Oct 09 06:26:34 AM UTC 24 519723864207 ps
T418 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.30477593 Oct 09 06:26:19 AM UTC 24 Oct 09 06:26:38 AM UTC 24 5555270547 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.179883855 Oct 09 06:24:28 AM UTC 24 Oct 09 06:26:39 AM UTC 24 166567240355 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.3052568929 Oct 09 06:12:27 AM UTC 24 Oct 09 06:26:44 AM UTC 24 139232744584 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.3728550265 Oct 09 06:19:44 AM UTC 24 Oct 09 06:26:46 AM UTC 24 162596434950 ps
T420 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.103423660 Oct 09 06:26:45 AM UTC 24 Oct 09 06:27:04 AM UTC 24 4188250546 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled.3558467344 Oct 09 06:22:14 AM UTC 24 Oct 09 06:27:12 AM UTC 24 487457459997 ps
T421 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.739811423 Oct 09 06:23:43 AM UTC 24 Oct 09 06:27:17 AM UTC 24 323169785215 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_clock_gating.3757655142 Oct 09 06:25:12 AM UTC 24 Oct 09 06:27:19 AM UTC 24 373460795975 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.1298886443 Oct 09 06:27:20 AM UTC 24 Oct 09 06:27:23 AM UTC 24 494386648 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.3704523763 Oct 09 06:15:10 AM UTC 24 Oct 09 06:27:28 AM UTC 24 319026725987 ps
T423 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.1467391862 Oct 09 06:12:54 AM UTC 24 Oct 09 06:27:33 AM UTC 24 330690147275 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1925251904 Oct 09 06:27:13 AM UTC 24 Oct 09 06:27:39 AM UTC 24 3608853573 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.4121980945 Oct 09 06:27:25 AM UTC 24 Oct 09 06:27:43 AM UTC 24 6095733813 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3299594198 Oct 09 06:08:58 AM UTC 24 Oct 09 06:27:51 AM UTC 24 332386041109 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_clock_gating.2185224237 Oct 09 06:26:39 AM UTC 24 Oct 09 06:27:54 AM UTC 24 359977112180 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.1289739356 Oct 09 06:17:31 AM UTC 24 Oct 09 06:28:03 AM UTC 24 95367074676 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.2928042629 Oct 09 06:19:24 AM UTC 24 Oct 09 06:28:38 AM UTC 24 80056535572 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.4208735592 Oct 09 06:22:23 AM UTC 24 Oct 09 06:28:41 AM UTC 24 163587358259 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.4191742407 Oct 09 06:23:00 AM UTC 24 Oct 09 06:28:47 AM UTC 24 337217797294 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_poweron_counter.2933558646 Oct 09 06:28:41 AM UTC 24 Oct 09 06:28:47 AM UTC 24 4178696293 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.2014851162 Oct 09 06:26:47 AM UTC 24 Oct 09 06:28:50 AM UTC 24 35093266607 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1074213637 Oct 09 06:13:54 AM UTC 24 Oct 09 06:28:50 AM UTC 24 600559345104 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.999991646 Oct 09 06:21:54 AM UTC 24 Oct 09 06:28:52 AM UTC 24 64444431661 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_alert_test.852604375 Oct 09 06:28:53 AM UTC 24 Oct 09 06:28:55 AM UTC 24 370354972 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.3686412384 Oct 09 06:13:23 AM UTC 24 Oct 09 06:28:59 AM UTC 24 379530949536 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.41556276 Oct 09 06:16:40 AM UTC 24 Oct 09 06:29:01 AM UTC 24 488195105650 ps
T431 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.920080078 Oct 09 06:28:51 AM UTC 24 Oct 09 06:29:01 AM UTC 24 2021412299 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_smoke.437132657 Oct 09 06:28:56 AM UTC 24 Oct 09 06:29:02 AM UTC 24 5839227625 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.2498815505 Oct 09 06:28:03 AM UTC 24 Oct 09 06:29:19 AM UTC 24 499705291819 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_polled.1323182730 Oct 09 06:26:19 AM UTC 24 Oct 09 06:29:27 AM UTC 24 162523024861 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3153131342 Oct 09 06:06:57 AM UTC 24 Oct 09 06:29:28 AM UTC 24 491949416904 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2770464397 Oct 09 06:27:44 AM UTC 24 Oct 09 06:29:59 AM UTC 24 162897627273 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled_fixed.1630898627 Oct 09 06:23:36 AM UTC 24 Oct 09 06:30:01 AM UTC 24 160583342870 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.3385576443 Oct 09 06:19:32 AM UTC 24 Oct 09 06:30:06 AM UTC 24 622599566068 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_08/adc_ctrl-sim-vcs/coverage/default/21.adc_ctrl_poweron_counter.2988238619 Oct 09 06:30:02 AM UTC 24 Oct 09 06:30:09 AM UTC 24 4746489321 ps
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