Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19110

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3214

1

T8

5

T13

4

T17

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16959

1

T1

20

T4

15

T5

20

auto[1]

5365

1

T13

4

T14

8

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	52	1			T8	5		T144	1		T199	1
values[1]	542	1			T17	15		T20	2		T49	2
values[2]	610	1			T21	2		T40	28		T138	1
values[3]	609	1			T41	1		T65	1		T200	9
values[4]	487	1			T127	13		T101	12		T102	20
values[5]	580	1			T65	2		T129	13		T126	19
values[6]	628	1			T13	4		T49	33		T148	1
values[7]	717	1			T16	1		T18	1		T22	6
values[8]	779	1			T20	1		T40	18		T128	19
values[9]	3219	1			T14	8		T15	4		T19	8
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	693	1			T8	5		T17	15		T20	2
values[1]	730	1			T21	2		T65	1		T138	1
values[2]	477	1			T41	1		T200	9		T102	20
values[3]	575	1			T127	13		T200	8		T100	9
values[4]	540	1			T65	2		T129	13		T126	19
values[5]	660	1			T13	4		T18	1		T49	33
values[6]	2852	1			T16	1		T19	8		T22	6
values[7]	688	1			T14	8		T20	1		T40	18
values[8]	827	1			T15	4		T129	19		T30	1
values[9]	172	1			T65	24		T165	8		T201	14
minimum	14110	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	1		T40	13		T129	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	4		T17	1		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T21	1		T65	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T138	1		T100	1		T188	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T102	12		T149	1		T143	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T41	1		T200	9		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T100	9		T101	1		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T127	7		T200	8		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T65	1		T126	10		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T129	13		T95	2		T163	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T126	10		T102	8		T203	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	3		T18	1		T49	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T16	1		T19	1		T49	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T22	4		T202	10		T204	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	6		T40	9		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T20	1		T128	9		T130	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T15	4		T129	19		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	1		T102	11		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T165	8		T201	1		T169	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T65	11		T205	1		T157	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13969	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T206	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	15		T98	13		T207	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T17	14		T49	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T21	1		T133	10		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T188	13		T209	9		T180	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T102	8		T87	11		T210	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T211	8		T185	11		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T101	11		T139	1		T213	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T127	6		T139	11		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T65	1		T126	9		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T95	14		T154	12		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T126	8		T102	9		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	1		T49	15		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	847	1			T19	7		T49	2		T151	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	2		T204	16		T134	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T14	2		T40	9		T215	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T128	10		T127	19		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T162	11		T216	9		T186	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T102	7		T217	9		T150	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T201	13		T169	11		T218	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T65	13		T157	13		T219	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T144	1		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T8	4		T220	6		T221	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T20	1		T129	19		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T20	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T21	1		T40	13		T133	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T138	1		T95	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T65	1		T149	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	1		T200	9		T211	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T101	1		T102	12		T222	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T127	7		T161	1		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T65	1		T126	10		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T129	13		T200	8		T95	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T126	10		T152	14		T203	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	3		T49	18		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	1		T49	6		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	1		T22	4		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	9		T224	1		T188	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T20	1		T128	9		T130	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1754	1			T14	6		T15	4		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T65	11		T30	1		T102	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T8	1		T220	5		T221	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T98	13		T207	6		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	14		T49	1		T132	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T21	1		T40	15		T133	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T95	13		T168	8		T226	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T208	2		T227	9		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T211	8		T188	13		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T101	11		T102	8		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T127	6		T223	4		T185	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T65	1		T126	9		T132	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T95	14		T139	11		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T126	8		T152	10		T208	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	1		T49	15		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	2		T102	9		T188	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	2		T140	11		T134	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T40	9		T188	8		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T128	10		T127	19		T204	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T14	2		T19	7		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	13		T102	7		T217	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	1		T40	16		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	4		T17	15		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T21	2		T65	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	1		T100	1		T188	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T102	9		T149	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T41	1		T200	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T100	1		T101	12		T139	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T127	7		T200	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T65	2		T126	10		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T129	1		T95	16		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T126	9		T102	10		T203	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	3		T18	1		T49	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T16	1		T19	8		T49	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T22	5		T202	1		T204	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	6		T40	10		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T20	1		T128	11		T130	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T15	4		T129	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T30	1		T102	8		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T165	1		T201	14		T169	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T65	14		T205	1		T157	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14103	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	12		T129	18		T225	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	1		T100	8		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T133	11		T208	2		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T188	15		T231	11		T180	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T102	11		T143	9		T87	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T200	8		T232	11		T185	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T100	8		T213	2		T233	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T127	6		T200	7		T139	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T126	9		T31	1		T152	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T129	12		T163	9		T234	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T126	9		T102	7		T203	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T49	17		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1221	1			T49	5		T50	14		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T22	1		T202	9		T204	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	2		T40	8		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T128	8		T127	13		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T129	18		T235	26		T203	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T102	10		T217	10		T150	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T165	7		T169	11		T236	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T65	10		T237	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T238	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T206	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T144	1		T199	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T8	4		T220	6		T221	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T20	1		T129	1		T98	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	15		T20	1		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T21	2		T40	16		T133	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	1		T95	14		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T65	1		T149	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T41	1		T200	1		T211	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T101	12		T102	9		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T127	7		T161	1		T223	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T65	2		T126	10		T31	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	1		T200	1		T95	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T126	9		T152	11		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	3		T49	16		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	1		T49	3		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T18	1		T22	5		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	10		T224	1		T188	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T20	1		T128	11		T130	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T14	6		T15	4		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T65	14		T30	1		T102	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T8	1		T220	5		T221	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T129	18		T225	6		T223	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T100	8		T132	9		T206	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	12		T133	11		T230	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T231	11		T69	1		T168	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T208	2		T143	9		T227	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T200	8		T188	15		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T102	11		T222	14		T210	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T127	6		T185	13		T233	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T126	9		T31	1		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T129	12		T200	7		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T126	9		T152	13		T203	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T49	17		T200	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	5		T102	7		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	1		T202	9		T140	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	8		T188	10		T229	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T128	8		T127	13		T204	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T14	2		T50	14		T51	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T65	10		T102	10		T217	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19272

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3052

1

T13

4

T17

15

T20

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17035

1

T1

20

T4

15

T5

20

auto[1]

5289

1

T13

4

T15

4

T17

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T240	12		T241	14		T210	16
values[0]	79	1			T102	20		T162	27		T242	32
values[1]	649	1			T18	1		T40	18		T130	2
values[2]	2594	1			T19	8		T21	2		T50	15
values[3]	647	1			T15	4		T16	1		T20	1
values[4]	750	1			T14	8		T40	28		T49	33
values[5]	591	1			T8	5		T20	1		T129	19
values[6]	634	1			T20	1		T41	1		T148	1
values[7]	586	1			T17	15		T65	1		T126	18
values[8]	601	1			T102	17		T149	1		T215	7
values[9]	1049	1			T13	4		T22	6		T49	10
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	849	1			T18	1		T130	2		T30	1
values[1]	2605	1			T19	8		T21	2		T40	18
values[2]	597	1			T16	1		T20	1		T40	28
values[3]	832	1			T8	5		T14	8		T15	4
values[4]	525	1			T20	1		T65	24		T243	4
values[5]	675	1			T20	1		T41	1		T148	1
values[6]	667	1			T17	15		T65	1		T215	7
values[7]	458	1			T13	4		T49	2		T102	17
values[8]	813	1			T22	6		T128	19		T65	2
values[9]	177	1			T49	8		T100	1		T202	1
minimum	14126	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T18	1		T130	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T130	1		T127	14		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T19	1		T21	1		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T200	8		T161	1		T244	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T16	1		T20	1		T127	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	13		T131	1		T150	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	4		T14	6		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T129	19		T200	9		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T243	4		T95	1		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T20	1		T65	11		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T148	1		T139	13		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T20	1		T41	1		T126	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T225	7		T188	16		T230	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	1		T65	1		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T102	8		T217	11		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	3		T49	1		T204	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T95	1		T100	9		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T22	4		T128	9		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T49	6		T100	1		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T203	8		T139	11		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13979	1			T1	20		T4	15		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T102	8		T162	15		T142	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	19		T98	13		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T19	7		T21	1		T40	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T244	1		T246	3		T241	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T127	6		T152	10		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	15		T150	16		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T14	2		T49	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T207	6		T140	4		T223	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T95	10		T47	1		T188	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T65	13		T101	11		T208	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T139	11		T133	10		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T126	8		T102	7		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T225	4		T188	13		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T17	14		T215	6		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T102	9		T217	9		T135	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	1		T49	1		T204	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T95	13		T132	3		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T22	2		T128	10		T65	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T49	2		T248	4		T249	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T139	9		T223	4		T209	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	2		T15	5		T22	9