Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

17062

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

5262

1

T8

5

T15

4

T19

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16743

1

T1

20

T4

15

T5

20

auto[1]

5581

1

T14

8

T18

1

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	307	1			T15	4		T47	6		T215	7
values[0]	37	1			T225	25		T276	12		-	-
values[1]	502	1			T13	4		T16	1		T18	1
values[2]	565	1			T129	19		T200	8		T149	2
values[3]	545	1			T17	15		T20	1		T49	10
values[4]	699	1			T22	6		T40	28		T65	24
values[5]	764	1			T41	1		T128	19		T65	1
values[6]	537	1			T65	2		T102	18		T203	9
values[7]	430	1			T14	8		T20	1		T21	2
values[8]	664	1			T8	5		T130	1		T131	1
values[9]	3173	1			T19	8		T20	1		T50	15
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	504	1			T13	4		T16	1		T49	33
values[1]	2567	1			T19	8		T50	15		T151	8
values[2]	643	1			T17	15		T20	1		T22	6
values[3]	655	1			T40	28		T130	1		T126	18
values[4]	745	1			T41	1		T128	19		T65	1
values[5]	444	1			T21	2		T65	2		T102	18
values[6]	661	1			T14	8		T20	1		T40	18
values[7]	586	1			T8	5		T127	33		T131	1
values[8]	911	1			T15	4		T20	1		T95	11
values[9]	298	1			T213	9		T163	10		T177	1
minimum	14310	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	3		T16	1		T95	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	18		T149	2		T281	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T200	8		T223	1		T183	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1481	1			T19	1		T50	15		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T17	1		T22	4		T65	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T20	1		T49	7		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	13		T130	1		T243	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T126	10		T127	7		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	1		T65	1		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T128	9		T143	10		T230	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T21	1		T102	11		T202	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T65	1		T161	1		T203	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	6		T20	1		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T40	9		T130	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T127	14		T200	5		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	4		T131	1		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T95	1		T101	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T15	4		T20	1		T152	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T213	3		T163	10		T279	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T177	1		T210	3		T272	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14068	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T225	14		T312	1		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	1		T95	4		T139	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T49	15		T251	10		T290	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T223	4		T183	3		T87	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	841	1			T19	7		T151	7		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	14		T22	2		T65	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T49	3		T217	9		T207	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T40	15		T102	9		T162	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T126	8		T127	6		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T95	13		T188	9		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T128	10		T230	12		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T21	1		T102	7		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T65	1		T257	1		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	2		T139	11		T188	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	9		T102	8		T150	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T127	19		T186	1		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T98	13		T230	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T95	10		T101	11		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T152	10		T140	11		T214	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T213	6		T279	10		T285	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T210	16		T272	6		T313	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	11		T248	15		T276	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T47	5		T215	1		T213	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T15	4		T234	4		T272	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	14		T276	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	3		T16	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T49	18		T149	1		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T200	8		T183	1		T233	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T129	19		T149	2		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	1		T126	10		T200	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T20	1		T49	7		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T22	4		T40	13		T65	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T126	10		T127	7		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T41	1		T65	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T128	9		T143	10		T229	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T102	11		T188	1		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T65	1		T203	9		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	6		T20	1		T21	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T40	9		T30	1		T102	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T32	2		T282	2		T188	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	4		T130	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T127	14		T200	5		T95	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1684	1			T19	1		T20	1		T50	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T47	1		T215	6		T213	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T272	6		T313	2		T92	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T225	11		T276	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T95	4		T139	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T49	15		T251	10		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T183	3		T271	8		T87	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T188	8		T162	11		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	14		T126	9		T223	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T49	3		T207	6		T132	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	2		T40	15		T65	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T126	8		T127	6		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T95	13		T142	2		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T128	10		T229	7		T288	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T102	7		T188	9		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T65	1		T230	12		T257	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T14	2		T21	1		T139	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	9		T102	8		T133	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T188	13		T277	1		T284	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T98	13		T150	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T127	19		T95	10		T101	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	992	1			T19	7		T151	7		T269	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	3		T16	1		T95	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T49	16		T149	2		T281	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T200	1		T223	5		T183	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1159	1			T19	8		T50	1		T151	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	15		T22	5		T65	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T20	1		T49	5		T217	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	16		T130	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T126	9		T127	7		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T41	1		T65	1		T95	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T128	11		T143	1		T230	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T21	2		T102	8		T202	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T65	2		T161	1		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	6		T20	1		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	10		T130	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T127	20		T200	1		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	4		T131	1		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T95	11		T101	12		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T15	4		T20	1		T152	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T213	7		T163	1		T279	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T177	1		T210	17		T272	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14154	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T225	12		T312	1		T178	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	1		T139	9		T135	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T49	17		T143	6		T275	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T200	7		T233	9		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1163	1			T50	14		T51	6		T253	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	1		T65	10		T126	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T49	5		T217	10		T132	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T40	12		T243	3		T102	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T126	9		T127	6		T100	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T206	21		T142	3		T212	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T128	8		T143	9		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T102	10		T202	9		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T203	8		T257	1		T86	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	2		T31	1		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	8		T102	11		T150	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	13		T200	4		T222	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	1		T232	1		T230	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	1		T232	11		T223	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T152	13		T140	12		T214	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T213	2		T163	9		T279	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T210	2		T272	6		T265	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T129	30		T235	20		T314	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T225	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T47	5		T215	7		T213	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T15	4		T234	1		T272	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T225	12		T276	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	3		T16	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T49	16		T149	1		T281	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T200	1		T183	4		T233	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T129	1		T149	2		T188	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	15		T126	10		T200	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T20	1		T49	5		T207	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T22	5		T40	16		T65	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T126	9		T127	7		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T41	1		T65	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T128	11		T143	1		T229	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T102	8		T188	10		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T65	2		T203	1		T58	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T14	6		T20	1		T21	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	10		T30	1		T102	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	2		T282	2		T188	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	4		T130	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T127	20		T200	1		T95	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1342	1			T19	8		T20	1		T50	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	1		T213	2		T229	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T234	3		T272	6		T313	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T225	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T129	30		T235	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T49	17		T143	6		T275	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T200	7		T233	9		T271	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T129	18		T188	10		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T126	9		T200	8		T100	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T49	5		T132	9		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T22	1		T40	12		T65	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T126	9		T127	6		T100	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T206	21		T142	3		T212	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T128	8		T143	9		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T102	10		T208	2		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T203	8		T230	14		T257	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T14	2		T31	1		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	8		T102	11		T203	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T188	15		T213	7		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T150	15		T134	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T127	13		T200	4		T232	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T50	14		T51	6		T253	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2