Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19301

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3023

1

T13

4

T14

8

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17020

1

T1

20

T4

15

T5

20

auto[1]

5304

1

T13

4

T14

8

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	39	1			T235	21		T315	1		T316	8
values[0]	44	1			T144	1		T308	9		T248	13
values[1]	601	1			T13	4		T15	4		T20	1
values[2]	736	1			T17	15		T49	33		T129	13
values[3]	752	1			T148	1		T138	1		T100	1
values[4]	2621	1			T19	8		T20	1		T50	15
values[5]	711	1			T49	8		T126	19		T101	12
values[6]	792	1			T8	5		T21	2		T40	28
values[7]	697	1			T14	8		T16	1		T40	18
values[8]	435	1			T20	1		T129	19		T200	8
values[9]	795	1			T18	1		T22	6		T41	1
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	764	1			T13	4		T15	4		T20	1
values[1]	756	1			T17	15		T49	33		T148	1
values[2]	862	1			T65	1		T95	5		T100	1
values[3]	2525	1			T19	8		T20	1		T50	15
values[4]	732	1			T8	5		T21	2		T49	10
values[5]	849	1			T40	28		T127	33		T200	9
values[6]	537	1			T14	8		T16	1		T40	18
values[7]	495	1			T20	1		T129	19		T102	17
values[8]	548	1			T18	1		T22	6		T41	1
values[9]	152	1			T65	24		T188	10		T143	10
minimum	14104	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T15	4		T20	1		T65	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	3		T126	10		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	18		T129	19		T200	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T17	1		T148	1		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T65	1		T95	1		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T100	1		T281	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T19	1		T50	15		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T128	9		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	4		T21	1		T49	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T162	14		T244	4		T230	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	13		T102	12		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T127	14		T200	9		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T130	1		T200	8		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	6		T16	1		T40	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T202	10		T140	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T20	1		T129	19		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	1		T130	1		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T18	1		T22	4		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T65	11		T188	1		T143	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T241	5		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13967	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T65	1		T209	9		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T126	8		T98	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	15		T215	6		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	14		T207	6		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T95	4		T152	10		T188	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T208	2		T239	13		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	787	1			T19	7		T151	7		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	10		T95	10		T101	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	1		T21	1		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T162	11		T244	1		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	15		T102	8		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T127	19		T150	16		T225	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T95	13		T102	7		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	2		T40	9		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T140	4		T209	6		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T102	9		T132	3		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T127	6		T139	1		T251	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	2		T139	8		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T65	13		T188	9		T319	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T241	10		T320	12		T316	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T235	21		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T315	1		T316	3		T321	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T144	1		T248	1		T322	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T308	9		T249	4		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	4		T20	1		T65	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	3		T131	1		T98	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	18		T200	5		T282	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	1		T129	13		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	14		T215	1		T212	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	1		T138	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1541	1			T19	1		T50	15		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T128	9		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	6		T126	10		T102	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T101	1		T150	16		T203	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	4		T21	1		T40	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T200	9		T149	1		T244	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T130	1		T100	9		T102	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	6		T16	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T200	8		T95	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	1		T129	19		T102	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T41	1		T65	11		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T18	1		T22	4		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T316	5		T321	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T249	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T65	1		T229	7		T154	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T13	1		T98	13		T217	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	15		T209	9		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T17	14		T126	8		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	10		T215	6		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T207	6		T188	8		T239	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	854	1			T19	7		T151	7		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T128	10		T95	10		T211	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	2		T126	9		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T101	11		T150	16		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T21	1		T40	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T244	1		T208	16		T86	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T102	7		T230	7		T251	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	2		T40	9		T127	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T95	13		T47	1		T209	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T102	9		T132	3		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T65	13		T127	6		T139	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T22	2		T139	8		T225	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	4		T20	1		T65	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	3		T126	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	16		T129	1		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T17	15		T148	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T65	1		T95	5		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T100	1		T281	1		T208	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1092	1			T19	8		T50	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T20	1		T128	11		T95	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T8	4		T21	2		T49	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T162	12		T244	3		T230	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	16		T102	9		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T127	20		T200	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T130	1		T200	1		T95	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	6		T16	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T202	1		T140	5		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T20	1		T129	1		T102	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T41	1		T130	1		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T18	1		T22	5		T139	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T65	14		T188	10		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T241	11		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14103	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T243	3		T31	1		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T126	9		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	17		T129	18		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T129	12		T140	12		T188	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T152	13		T203	8		T188	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T208	2		T239	5		T233	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T50	14		T51	6		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T128	8		T143	14		T186	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T49	5		T126	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T162	13		T244	2		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T40	12		T102	11		T162	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T127	13		T200	8		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T200	7		T100	8		T102	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	2		T40	8		T206	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T202	9		T153	9		T222	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T129	18		T102	7		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T127	6		T100	8		T235	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	1		T139	9		T225	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T65	10		T143	9		T305	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T241	4		T320	13		T316	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T235	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T315	1		T316	6		T321	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T144	1		T248	13		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T308	1		T249	3		T323	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	4		T20	1		T65	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	3		T131	1		T98	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	16		T200	1		T282	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	15		T129	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T152	11		T215	7		T212	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T148	1		T138	1		T100	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T19	8		T50	1		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T20	1		T128	11		T95	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T49	3		T126	10		T102	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T101	12		T150	17		T203	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	4		T21	2		T40	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T200	1		T149	1		T244	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T130	1		T100	1		T102	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	6		T16	1		T40	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T200	1		T95	14		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T20	1		T129	1		T102	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T41	1		T65	14		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T18	1		T22	5		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T235	20		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T316	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T322	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T308	8		T249	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T129	18		T243	3		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	1		T217	10		T257	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	17		T200	4		T143	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T129	12		T126	9		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	13		T212	3		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T188	10		T239	5		T229	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T50	14		T51	6		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T128	8		T208	2		T233	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	5		T126	9		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	15		T203	7		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T40	12		T132	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T200	8		T244	2		T208	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T100	8		T102	10		T235	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	2		T40	8		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T200	7		T47	1		T213	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T129	18		T102	7		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T65	10		T127	6		T100	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	1		T139	9		T225	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2