Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19177

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3147

1

T14

8

T15

4

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16914

1

T1

20

T4

15

T5

20

auto[1]

5410

1

T16

1

T18

1

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	327	1			T126	19		T127	13		T95	14
values[0]	22	1			T20	1		T100	1		T282	2
values[1]	735	1			T22	6		T65	2		T130	2
values[2]	556	1			T13	4		T14	8		T41	1
values[3]	698	1			T148	1		T128	19		T31	3
values[4]	757	1			T127	33		T206	22		T225	11
values[5]	2532	1			T16	1		T18	1		T19	8
values[6]	680	1			T17	15		T20	1		T40	28
values[7]	563	1			T40	18		T49	8		T65	24
values[8]	716	1			T20	1		T49	33		T200	8
values[9]	637	1			T8	5		T15	4		T21	2
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	761	1			T14	8		T20	1		T22	6
values[1]	599	1			T13	4		T41	1		T148	1
values[2]	683	1			T128	19		T127	33		T31	3
values[3]	2735	1			T19	8		T50	15		T151	8
values[4]	474	1			T16	1		T18	1		T40	28
values[5]	735	1			T17	15		T20	1		T129	32
values[6]	557	1			T40	18		T49	8		T65	24
values[7]	624	1			T20	1		T49	33		T200	8
values[8]	710	1			T15	4		T21	2		T65	1
values[9]	153	1			T8	5		T32	2		T281	1
minimum	14293	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	1		T130	2		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	6		T20	1		T22	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	3		T132	10		T162	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	1		T148	1		T235	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	14		T31	3		T95	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T128	9		T101	1		T133	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T19	1		T50	15		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	5		T184	1		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	1		T102	12		T206	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	1		T40	13		T200	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T20	1		T129	19		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	1		T129	13		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T40	9		T49	6		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T65	11		T149	1		T34	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T49	18		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T200	8		T98	1		T235	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T126	10		T95	1		T100	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T15	4		T21	1		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T8	4		T32	2		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T229	11		T324	1		T258	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14039	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T152	14		T222	17		T325	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T132	1		T215	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	2		T22	2		T65	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T132	3		T162	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T225	11		T204	16		T251	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	19		T95	4		T211	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	10		T101	11		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T19	7		T151	7		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T135	3		T213	6		T266	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T102	8		T288	10		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T40	15		T95	10		T205	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T140	11		T223	4		T142	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	14		T126	8		T207	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T40	9		T49	2		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T65	13		T244	1		T208	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T49	15		T47	1		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	4		T142	2		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T126	9		T95	13		T102	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T21	1		T127	6		T98	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T8	1		T134	15		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T229	12		T258	2		T237	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T152	10		T326	9		T327	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T126	10		T95	1		T149	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T127	7		T98	1		T100	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T100	1		T282	2		T302	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T20	1		T318	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T130	2		T138	1		T132	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T22	4		T65	1		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	3		T49	1		T132	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	6		T41	1		T235	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T31	3		T95	1		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	1		T128	9		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T127	14		T206	22		T225	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T184	1		T213	3		T239	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T18	1		T19	1		T50	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T16	1		T200	5		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	1		T129	19		T243	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T17	1		T40	13		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T40	9		T49	6		T203	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T65	11		T149	1		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T49	18		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T200	8		T98	1		T235	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	4		T100	9		T102	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T15	4		T21	1		T65	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T126	9		T95	13		T181	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T127	6		T98	13		T188	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T132	1		T215	6		T162	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	2		T65	1		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	1		T49	1		T132	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T14	2		T139	8		T225	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T95	4		T211	8		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T128	10		T101	11		T133	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T127	19		T225	4		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T213	6		T239	13		T230	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	819	1			T19	7		T151	7		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T95	10		T135	3		T201	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T102	8		T140	11		T223	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	14		T40	15		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	9		T49	2		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T65	13		T223	5		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	15		T47	1		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	4		T208	16		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	1		T102	9		T134	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T21	1		T102	7		T188	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T49	2		T130	2		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	6		T20	1		T22	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	3		T132	4		T162	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T41	1		T148	1		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T127	20		T31	2		T95	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T128	11		T101	12		T133	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T19	8		T50	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	4		T184	1		T213	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	1		T102	9		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	1		T40	16		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T20	1		T129	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	15		T129	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T40	10		T49	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T65	14		T149	1		T34	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T20	1		T49	16		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T200	1		T98	1		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T126	10		T95	14		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T15	4		T21	2		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T8	4		T32	2		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T229	13		T324	1		T258	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14147	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T152	11		T222	1		T325	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	12		T214	17		T185	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	2		T22	1		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	1		T132	9		T162	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T235	20		T202	9		T225	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T127	13		T31	1		T206	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T128	8		T133	11		T216	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T50	14		T51	6		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T135	4		T213	2		T222	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T102	11		T206	4		T213	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	12		T200	4		T231	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	18		T243	3		T203	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T129	12		T126	9		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T40	8		T49	5		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T65	10		T244	2		T208	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	17		T47	1		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T200	7		T235	6		T203	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T126	9		T100	8		T102	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T127	6		T200	8		T100	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T8	1		T134	16		T275	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T229	10		T237	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T162	11		T234	11		T291	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T152	13		T222	16		T325	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T126	10		T95	14		T149	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T127	7		T98	14		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T100	1		T282	2		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T20	1		T318	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T130	2		T138	1		T132	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	5		T65	2		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	3		T49	2		T132	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	6		T41	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	2		T95	5		T211	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	1		T128	11		T101	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T127	20		T206	1		T225	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T184	1		T213	7		T239	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T18	1		T19	8		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	1		T200	1		T95	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	1		T129	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	15		T40	16		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	10		T49	3		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T65	14		T149	1		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T20	1		T49	16		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T200	1		T98	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	4		T100	1		T102	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	4		T21	2		T65	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T126	9		T275	9		T328	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T127	6		T100	8		T188	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T302	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	12		T162	11		T214	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	1		T152	13		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T132	9		T162	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T14	2		T235	20		T139	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	1		T204	2		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T128	8		T202	9		T133	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	13		T206	21		T225	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T213	2		T239	5		T230	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T50	14		T51	6		T253	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T200	4		T135	4		T231	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T129	18		T243	3		T102	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	12		T129	12		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	8		T49	5		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T65	10		T223	5		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	17		T47	1		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T200	7		T235	6		T203	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	1		T100	8		T102	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T200	8		T102	10		T188	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2