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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22324 1 T1 20 T4 15 T5 20



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 19208 1 T1 20 T4 15 T5 20
auto[ADC_CTRL_FILTER_COND_OUT] 3116 1 T8 5 T13 4 T17 15



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16828 1 T1 20 T4 15 T5 20
auto[1] 5496 1 T13 4 T14 8 T16 1



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18852 1 T1 20 T4 15 T5 20
auto[1] 3472 1 T8 1 T13 1 T14 4



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 328 1 T65 24 T131 1 T102 18
values[0] 32 1 T8 5 T144 1 T199 1
values[1] 604 1 T17 15 T20 2 T40 28
values[2] 600 1 T21 2 T65 1 T138 1
values[3] 533 1 T41 1 T200 9 T149 1
values[4] 521 1 T127 13 T200 8 T101 12
values[5] 606 1 T65 2 T129 13 T126 19
values[6] 635 1 T13 4 T49 33 T148 1
values[7] 690 1 T16 1 T18 1 T22 6
values[8] 807 1 T20 1 T40 18 T128 19
values[9] 2867 1 T14 8 T15 4 T19 8
minimum 14101 1 T1 20 T4 15 T5 20



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 514 1 T20 2 T40 28 T49 2
values[1] 699 1 T21 2 T65 1 T138 1
values[2] 466 1 T41 1 T200 9 T149 1
values[3] 622 1 T127 13 T200 8 T100 9
values[4] 528 1 T65 2 T129 13 T126 19
values[5] 644 1 T13 4 T18 1 T49 33
values[6] 2892 1 T16 1 T19 8 T22 6
values[7] 693 1 T14 8 T20 1 T40 18
values[8] 829 1 T15 4 T129 19 T30 1
values[9] 141 1 T65 24 T165 8 T201 14
minimum 14296 1 T1 20 T4 15 T5 20



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 18375 1 T1 20 T4 15 T5 20
auto[1] 3949 1 T8 1 T13 1 T14 2



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T20 1 T40 13 T129 19
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T20 1 T49 1 T95 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 227 1 T21 1 T65 1 T133 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T138 1 T100 1 T202 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T149 1 T143 10 T212 4
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T41 1 T200 9 T211 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T100 9 T101 1 T102 12
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T127 7 T200 8 T161 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T65 1 T126 10 T31 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T129 13 T95 2 T288 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T126 10 T243 4 T102 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 185 1 T13 3 T18 1 T49 18
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1564 1 T16 1 T19 1 T49 6
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 261 1 T22 4 T202 10 T204 22
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 188 1 T14 6 T40 9 T224 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 216 1 T20 1 T128 9 T130 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 317 1 T15 4 T129 19 T131 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T30 1 T102 11 T149 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 53 1 T165 8 T201 1 T236 6
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 23 1 T65 11 T205 1 T157 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14008 1 T1 20 T4 15 T5 20
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 50 1 T8 4 T17 1 T132 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T40 15 T98 13 T225 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 85 1 T49 1 T95 13 T180 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 162 1 T21 1 T133 10 T208 2
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T186 11 T295 6 T226 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 97 1 T212 4 T87 11 T210 16
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 98 1 T211 8 T188 13 T185 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T101 11 T102 8 T139 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T127 6 T139 11 T140 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 88 1 T65 1 T126 9 T152 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T95 14 T288 10 T154 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T126 8 T102 9 T188 9
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T13 1 T49 15 T214 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 853 1 T19 7 T49 2 T151 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T22 2 T204 16 T134 15
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T14 2 T40 9 T215 6
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T128 10 T127 19 T47 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T162 11 T216 9 T186 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T102 7 T217 9 T150 16
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 28 1 T201 13 T218 15 - -
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 37 1 T65 13 T157 13 T237 11
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 164 1 T14 2 T15 5 T22 9
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 74 1 T8 1 T17 14 T132 3



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 102 1 T131 1 T235 28 T204 3
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 84 1 T65 11 T102 11 T217 11
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T199 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 12 1 T8 4 T144 1 T220 6
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T20 1 T40 13 T129 19
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 151 1 T17 1 T20 1 T49 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T21 1 T65 1 T133 12
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T138 1 T100 1 T202 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T149 1 T208 3 T183 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T41 1 T200 9 T211 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T101 1 T102 12 T139 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 144 1 T127 7 T200 8 T161 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T65 1 T126 10 T31 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T129 13 T95 2 T139 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T126 10 T243 4 T152 14
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T13 3 T49 18 T148 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 182 1 T16 1 T49 6 T98 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T18 1 T22 4 T202 10
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 191 1 T40 9 T224 1 T188 11
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 262 1 T20 1 T128 9 T130 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1681 1 T14 6 T15 4 T19 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T30 1 T150 16 T206 22
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 13965 1 T1 20 T4 15 T5 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 61 1 T251 19 T261 1 T201 13
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 81 1 T65 13 T102 7 T217 9
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T8 1 T220 5 T327 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T40 15 T98 13 T207 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T17 14 T49 1 T95 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T21 1 T133 10 T230 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T186 11 T168 8 T295 6
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 126 1 T208 2 T209 9 T271 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 95 1 T211 8 T188 13 T153 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 96 1 T101 11 T102 8 T139 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T127 6 T223 4 T185 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 88 1 T65 1 T126 9 T132 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T95 14 T139 11 T140 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 140 1 T126 8 T152 10 T208 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T13 1 T49 15 T185 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 101 1 T49 2 T102 9 T188 9
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T22 2 T140 11 T134 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T40 9 T188 8 T162 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T128 10 T127 19 T47 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 907 1 T14 2 T19 7 T151 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 122 1 T150 16 T225 11 T329 3
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 136 1 T14 2 T15 5 T22 9



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T20 1 T40 16 T129 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 104 1 T20 1 T49 2 T95 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T21 2 T65 1 T133 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T138 1 T100 1 T202 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T149 1 T143 1 T212 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T41 1 T200 1 T211 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T100 1 T101 12 T102 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 169 1 T127 7 T200 1 T161 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 115 1 T65 2 T126 10 T31 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 160 1 T129 1 T95 16 T288 11
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T126 9 T243 1 T102 10
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T13 3 T18 1 T49 16
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1180 1 T16 1 T19 8 T49 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T22 5 T202 1 T204 17
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T14 6 T40 10 T224 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T20 1 T128 11 T130 2
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 252 1 T15 4 T129 1 T131 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 177 1 T30 1 T102 8 T149 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 33 1 T165 1 T201 14 T236 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 41 1 T65 14 T205 1 T157 14
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14144 1 T1 20 T4 15 T5 20
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 95 1 T8 4 T17 15 T132 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T40 12 T129 18 T225 6
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 111 1 T100 8 T206 4 T180 12
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T133 11 T208 2 T230 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T231 11 T186 9 T69 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 102 1 T143 9 T212 3 T87 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 116 1 T200 8 T188 15 T232 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T100 8 T102 11 T139 9
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T127 6 T200 7 T139 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T126 9 T31 1 T152 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T129 12 T163 9 T199 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T126 9 T243 3 T102 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T13 1 T49 17 T200 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1237 1 T49 5 T50 14 T51 6
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T22 1 T202 9 T204 21
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T14 2 T40 8 T229 7
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T128 8 T127 13 T47 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 255 1 T129 18 T235 26 T203 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T102 10 T217 10 T150 15
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 48 1 T165 7 T236 5 T218 19
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T65 10 T237 9 - -
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 28 1 T238 2 T330 2 T331 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 29 1 T8 1 T132 9 T246 3



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 77 1 T131 1 T235 2 T204 1
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 96 1 T65 14 T102 8 T217 10
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 1 1 T199 1 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 25 1 T8 4 T144 1 T220 6
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T20 1 T40 16 T129 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T17 15 T20 1 T49 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 150 1 T21 2 T65 1 T133 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T138 1 T100 1 T202 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T149 1 T208 3 T183 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 115 1 T41 1 T200 1 T211 9
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T101 12 T102 9 T139 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T127 7 T200 1 T161 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 120 1 T65 2 T126 10 T31 2
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 188 1 T129 1 T95 16 T139 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T126 9 T243 1 T152 11
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T13 3 T49 16 T148 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T16 1 T49 3 T98 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 245 1 T18 1 T22 5 T202 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T40 10 T224 1 T188 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 263 1 T20 1 T128 11 T130 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1263 1 T14 6 T15 4 T19 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 152 1 T30 1 T150 17 T206 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 14101 1 T1 20 T4 15 T5 20
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 86 1 T235 26 T204 2 T232 1
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 69 1 T65 10 T102 10 T217 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 6 1 T8 1 T220 5 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 129 1 T40 12 T129 18 T225 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 121 1 T100 8 T132 9 T206 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T133 11 T230 14 T231 5
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 118 1 T231 11 T186 9 T69 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T208 2 T143 9 T271 3
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T200 8 T188 15 T232 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T102 11 T212 3 T222 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T127 6 T200 7 T185 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T126 9 T31 1 T100 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 179 1 T129 12 T139 12 T233 14
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T126 9 T243 3 T152 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T13 1 T49 17 T200 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T49 5 T102 7 T155 1
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T22 1 T202 9 T140 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T40 8 T188 10 T162 11
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T128 8 T127 13 T47 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1325 1 T14 2 T50 14 T51 6
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T150 15 T206 21 T225 13



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 18375 1 T1 20 T4 15 T5 20
auto[1] auto[0] 3949 1 T8 1 T13 1 T14 2

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