Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18992

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3332

1

T8

5

T14

8

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16680

1

T1

20

T4

15

T5

20

auto[1]

5644

1

T8

5

T13

4

T14

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	391	1			T15	2		T46	1		T30	3
values[0]	57	1			T230	17		T283	13		T178	18
values[1]	525	1			T40	18		T49	33		T126	19
values[2]	2732	1			T17	15		T19	8		T20	1
values[3]	543	1			T49	2		T130	1		T100	1
values[4]	634	1			T13	4		T16	1		T21	2
values[5]	594	1			T20	2		T30	1		T127	33
values[6]	645	1			T14	8		T49	8		T200	8
values[7]	646	1			T15	4		T41	1		T98	15
values[8]	636	1			T8	5		T65	24		T129	13
values[9]	1192	1			T18	1		T148	1		T65	3
minimum	13729	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T17	15		T20	1		T40	18
values[1]	2688	1			T19	8		T50	15		T151	8
values[2]	466	1			T49	2		T129	19		T101	12
values[3]	755	1			T13	4		T16	1		T22	6
values[4]	621	1			T14	8		T20	2		T21	2
values[5]	579	1			T15	4		T41	1		T98	1
values[6]	636	1			T8	5		T49	8		T95	11
values[7]	675	1			T65	1		T129	13		T200	9
values[8]	922	1			T18	1		T148	1		T65	26
values[9]	121	1			T127	13		T206	5		T245	10
minimum	14144	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	1		T49	18		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	1		T40	9		T95	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T19	1		T50	15		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T130	1		T200	5		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	1		T281	1		T212	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T129	19		T101	1		T235	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	3		T16	1		T129	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	4		T40	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	1		T127	14		T200	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	6		T20	1		T21	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	1		T98	1		T150	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	4		T102	11		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T95	1		T217	11		T282	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	4		T49	6		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T65	1		T129	13		T200	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T132	23		T206	22		T139	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T65	1		T130	1		T100	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T18	1		T148	1		T65	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T206	5		T153	12		T234	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T127	7		T245	1		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13970	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T178	18		T252	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	15		T214	16		T230	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	14		T40	9		T95	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T19	7		T151	7		T128	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T140	11		T162	11		T229	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T49	1		T212	4		T290	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T101	11		T211	8		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	1		T188	8		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	2		T40	15		T126	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T127	19		T102	9		T204	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	2		T21	1		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T150	16		T208	18		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T102	7		T207	6		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T95	10		T217	9		T134	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T49	2		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T152	10		T215	6		T135	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	4		T139	11		T209	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T65	1		T139	1		T266	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T65	13		T102	8		T139	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T153	12		T289	12		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T127	6		T245	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T252	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T15	2		T46	1		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T230	10		T336	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T283	1		T178	18		T337	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	18		T126	10		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	9		T200	5		T95	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T19	1		T20	1		T50	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T17	1		T225	7		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T281	1		T239	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T130	1		T100	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	3		T16	1		T129	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T21	1		T22	4		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	1		T127	14		T235	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	1		T30	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T200	8		T102	8		T150	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	6		T49	6		T213	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T41	1		T98	1		T100	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T15	4		T98	1		T102	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T129	13		T200	9		T95	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	4		T65	11		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T65	2		T130	1		T100	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T18	1		T148	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13593	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T230	7		T336	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T283	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	15		T126	9		T214	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T40	9		T95	17		T227	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	884	1			T19	7		T151	7		T128	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	14		T225	4		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T49	1		T239	13		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T101	11		T211	8		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	1		T188	8		T230	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T21	1		T22	2		T40	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T127	19		T204	16		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T188	9		T180	14		T246	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T102	9		T150	16		T208	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	2		T49	2		T213	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T217	9		T134	15		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T98	13		T102	7		T207	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T95	10		T152	10		T135	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	1		T65	13		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T65	1		T215	6		T139	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T127	6		T102	8		T139	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T20	1		T49	16		T31	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T17	15		T40	10		T95	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T19	8		T50	1		T151	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T130	1		T200	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T49	2		T281	1		T212	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	1		T101	12		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	3		T16	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	5		T40	16		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	1		T127	20		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	6		T20	1		T21	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T41	1		T98	1		T150	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	4		T102	8		T207	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T95	11		T217	10		T282	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	4		T49	3		T98	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T65	1		T129	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T132	6		T206	1		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T65	2		T130	1		T100	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T18	1		T148	1		T65	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T206	1		T153	13		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T127	7		T245	10		T286	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14104	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T178	1		T252	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	17		T31	1		T214	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	8		T225	6		T143	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T50	14		T51	6		T128	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T200	4		T140	12		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T212	3		T291	4		T338	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T129	18		T235	6		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	1		T129	18		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	1		T40	12		T126	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T127	13		T200	7		T102	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	2		T233	9		T180	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	15		T232	11		T208	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T102	10		T233	14		T231	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T217	10		T134	16		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T49	5		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T129	12		T200	8		T100	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T132	21		T206	21		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T100	8		T203	15		T271	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T65	10		T243	3		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T206	4		T153	11		T234	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T127	6		T339	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T204	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T178	17		T252	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T15	2		T46	1		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T293	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T230	8		T336	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T283	13		T178	1		T337	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	16		T126	10		T31	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	10		T200	1		T95	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T19	8		T20	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	15		T225	5		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T49	2		T281	1		T239	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	1		T100	1		T101	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	3		T16	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T21	2		T22	5		T40	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T20	1		T127	20		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T20	1		T30	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T200	1		T102	10		T150	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	6		T49	3		T213	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T41	1		T98	1		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	4		T98	14		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T129	1		T200	1		T95	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	4		T65	14		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T65	3		T130	1		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T18	1		T148	1		T138	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13729	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T289	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T230	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T178	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T49	17		T126	9		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	8		T200	4		T143	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T50	14		T51	6		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T225	6		T140	12		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T239	5		T212	3		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T229	24		T231	8		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	1		T129	18		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	1		T40	12		T129	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	13		T235	20		T204	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T232	1		T180	12		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T200	7		T102	7		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	2		T49	5		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T100	8		T217	10		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T102	10		T47	1		T206	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T129	12		T200	8		T152	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T65	10		T132	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T100	8		T206	4		T203	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T127	6		T243	3		T102	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2