Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19265

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3059

1

T13

4

T14

8

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16997

1

T1

20

T4

15

T5

20

auto[1]

5327

1

T13

4

T14

8

T16

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	227	1			T18	1		T65	24		T225	11
values[0]	29	1			T144	1		T248	13		T340	14
values[1]	580	1			T13	4		T15	4		T20	1
values[2]	767	1			T17	15		T49	33		T129	19
values[3]	826	1			T148	1		T129	13		T138	1
values[4]	2574	1			T19	8		T20	1		T50	15
values[5]	625	1			T8	5		T21	2		T49	8
values[6]	879	1			T40	28		T49	2		T200	9
values[7]	664	1			T14	8		T16	1		T40	18
values[8]	483	1			T20	1		T200	8		T95	14
values[9]	569	1			T22	6		T41	1		T129	19
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	551	1			T13	4		T20	1		T65	2
values[1]	720	1			T17	15		T49	33		T148	1
values[2]	876	1			T20	1		T65	1		T100	1
values[3]	2589	1			T19	8		T50	15		T151	8
values[4]	728	1			T8	5		T21	2		T49	10
values[5]	823	1			T40	28		T127	33		T200	9
values[6]	539	1			T14	8		T16	1		T40	18
values[7]	494	1			T20	1		T129	19		T102	17
values[8]	598	1			T18	1		T22	6		T41	1
values[9]	101	1			T65	24		T188	10		T305	10
minimum	14305	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T20	1		T65	1		T243	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	3		T126	10		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	18		T129	19		T200	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	1		T148	1		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T65	1		T152	14		T203	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T20	1		T100	1		T188	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T19	1		T50	15		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T128	9		T95	1		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	4		T21	1		T49	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	16		T162	14		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T40	13		T102	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T127	14		T200	9		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T130	1		T200	8		T95	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	6		T16	1		T40	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T202	10		T140	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	1		T129	19		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T41	1		T130	1		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	1		T22	4		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T65	11		T188	1		T305	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T241	5		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14029	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T217	11		T224	1		T257	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T65	1		T209	9		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T13	1		T126	8		T180	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	15		T215	6		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T17	14		T98	13		T207	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T152	10		T188	13		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T188	8		T208	2		T239	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	800	1			T19	7		T151	7		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T128	10		T95	10		T101	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T21	1		T49	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T150	16		T162	11		T230	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	15		T102	8		T132	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T127	19		T225	11		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T95	13		T102	7		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	2		T40	9		T133	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T140	4		T209	6		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T102	9		T132	3		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	6		T139	1		T251	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T22	2		T139	8		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T65	13		T188	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T241	10		T320	12		T341	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T217	9		T257	1		T245	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T65	11		T188	1		T232	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T18	1		T225	7		T233	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T144	1		T248	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T340	7		T323	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	4		T20	1		T65	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	3		T131	1		T217	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	18		T129	19		T200	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	1		T30	1		T126	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T152	14		T203	9		T188	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	1		T129	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1504	1			T19	1		T50	15		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T20	1		T128	9		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	4		T21	1		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T101	1		T162	14		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T40	13		T49	1		T102	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T200	9		T149	1		T150	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T130	1		T100	9		T102	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	6		T16	1		T40	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T200	8		T95	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T20	1		T102	8		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T41	1		T130	1		T127	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T22	4		T129	19		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T65	13		T188	9		T251	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T225	4		T241	10		T308	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T248	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T340	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T65	1		T209	9		T229	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T13	1		T217	9		T257	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	15		T215	6		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	14		T126	8		T98	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T152	10		T188	13		T223	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T188	8		T239	13		T229	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	825	1			T19	7		T151	7		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T128	10		T95	10		T211	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	1		T21	1		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T101	11		T162	11		T230	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	15		T49	1		T102	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T150	16		T244	1		T208	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T102	7		T230	7		T251	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	2		T40	9		T127	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T95	13		T47	1		T209	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T102	9		T132	3		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T127	6		T139	1		T140	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	2		T139	8		T214	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	1		T65	2		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	3		T126	9		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	16		T129	1		T200	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T17	15		T148	1		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T65	1		T152	11		T203	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T20	1		T100	1		T188	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T19	8		T50	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T128	11		T95	11		T101	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	4		T21	2		T49	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T150	17		T162	12		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	16		T102	9		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T127	20		T200	1		T98	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T130	1		T200	1		T95	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	6		T16	1		T40	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T202	1		T140	5		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	1		T129	1		T102	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T41	1		T130	1		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	1		T22	5		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T65	14		T188	10		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T241	11		T317	1		T318	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14129	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T217	10		T224	1		T257	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T243	3		T31	1		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T13	1		T126	9		T164	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	17		T129	18		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T129	12		T140	12		T134	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T152	13		T203	8		T188	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T188	10		T208	2		T239	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T50	14		T51	6		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T128	8		T216	2		T186	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T49	5		T126	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T150	15		T162	13		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	12		T102	11		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T127	13		T200	8		T203	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T200	7		T100	8		T102	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	2		T40	8		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T202	9		T153	9		T222	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T129	18		T102	7		T132	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	6		T100	8		T235	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T22	1		T139	9		T225	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T65	10		T305	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T241	4		T320	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T231	5		T256	16		T342	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T217	10		T257	1		T168	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T65	14		T188	10		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T18	1		T225	5		T233	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T144	1		T248	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T340	8		T323	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	4		T20	1		T65	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	3		T131	1		T217	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	16		T129	1		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T17	15		T30	1		T126	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T152	11		T203	1		T188	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	1		T129	1		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1141	1			T19	8		T50	1		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	1		T128	11		T95	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	4		T21	2		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T101	12		T162	12		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T40	16		T49	2		T102	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T200	1		T149	1		T150	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T130	1		T100	1		T102	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	6		T16	1		T40	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T200	1		T95	14		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T20	1		T102	10		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T41	1		T130	1		T127	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	5		T129	1		T32	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T65	10		T232	1		T251	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T225	6		T233	9		T241	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T340	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T243	3		T31	1		T229	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T13	1		T217	10		T257	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T49	17		T129	18		T200	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T126	9		T140	12		T134	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T152	13		T203	8		T188	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T129	12		T188	10		T239	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T50	14		T51	6		T253	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T128	8		T216	2		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T49	5		T126	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T162	13		T143	14		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T40	12		T102	11		T132	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T200	8		T150	15		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T100	8		T102	10		T235	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	2		T40	8		T127	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T200	7		T47	1		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T102	7		T132	9		T206	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T127	6		T100	8		T235	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	1		T129	18		T139	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2