Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T240	12		T241	8		T210	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T102	12		T162	12		T242	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T18	1		T40	9		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T130	1		T127	14		T200	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T19	1		T21	1		T50	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T235	21		T161	1		T244	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	4		T16	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T131	1		T150	16		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	6		T49	18		T95	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T40	13		T31	3		T206	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	4		T243	4		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T20	1		T129	19		T200	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T148	1		T203	9		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T41	1		T65	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T217	11		T133	12		T188	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T17	1		T65	1		T126	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T102	8		T225	7		T135	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T149	1		T215	1		T204	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T49	6		T95	1		T100	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T13	3		T22	4		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T241	6		T210	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T102	8		T162	15		T242	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	9		T162	11		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	19		T98	13		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T19	7		T21	1		T151	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T244	1		T229	12		T246	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T127	6		T152	10		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T150	16		T140	4		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T14	2		T49	15		T95	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	15		T223	5		T185	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T8	1		T95	10		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T101	11		T207	6		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	11		T183	3		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	13		T102	7		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T217	9		T133	10		T188	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T17	14		T126	8		T140	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T102	9		T225	4		T135	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T215	6		T204	16		T239	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	2		T95	13		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T13	1		T22	2		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T18	1		T130	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T130	1		T127	20		T98	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1191	1			T19	8		T21	2		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T200	1		T161	1		T244	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T16	1		T20	1		T127	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	16		T131	1		T150	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	4		T14	6		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T129	1		T200	1		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T243	1		T95	11		T98	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T20	1		T65	14		T101	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T148	1		T139	12		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	1		T41	1		T126	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T225	5		T188	14		T230	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T17	15		T65	1		T215	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T102	10		T217	10		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	3		T49	2		T204	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T95	14		T100	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T22	5		T128	11		T65	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T49	3		T100	1		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T203	1		T139	11		T223	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14113	1			T1	20		T4	15		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T100	8		T102	11		T235	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T127	13		T235	20		T204	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T40	8		T50	14		T51	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T200	7		T244	2		T231	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T127	6		T200	4		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	12		T150	15		T206	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	1		T14	2		T49	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T129	18		T200	8		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T243	3		T47	1		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T65	10		T208	13		T250	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	12		T133	11		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T126	9		T102	10		T202	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T225	6		T188	15		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T140	12		T232	11		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T102	7		T217	10		T135	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	1		T204	21		T222	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T100	8		T132	9		T225	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T22	1		T128	8		T232	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T49	5		T249	3		T252	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T203	7		T139	9		T212	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T162	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T240	1		T241	7		T210	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T102	9		T162	16		T242	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	1		T40	10		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	1		T127	20		T200	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T19	8		T21	2		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T235	1		T161	1		T244	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	4		T16	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T131	1		T150	17		T140	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	6		T49	16		T95	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T40	16		T31	2		T206	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	4		T243	1		T95	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T129	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T148	1		T203	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	1		T41	1		T65	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T217	10		T133	11		T188	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T17	15		T65	1		T126	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T102	10		T225	5		T135	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T149	1		T215	7		T204	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T49	3		T95	14		T100	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T13	3		T22	5		T49	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T240	11		T241	7		T210	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T102	11		T162	11		T242	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	8		T162	13		T142	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T127	13		T200	7		T204	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T50	14		T51	6		T253	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T235	20		T244	2		T233	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T129	18		T127	6		T200	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T150	15		T234	10		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	2		T49	17		T132	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	12		T31	1		T206	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T243	3		T47	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T129	18		T200	8		T185	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T203	8		T139	12		T155	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T65	10		T102	10		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T217	10		T133	11		T188	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T126	9		T140	12		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T102	7		T225	6		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T204	21		T232	11		T239	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T49	5		T100	8		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	1		T22	1		T128	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2