Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19256

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3068

1

T13

4

T17

15

T20

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16991

1

T1

20

T4

15

T5

20

auto[1]

5333

1

T13

4

T15

4

T17

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	309	1			T65	2		T100	1		T224	1
values[1]	708	1			T18	1		T130	2		T30	1
values[2]	2636	1			T19	8		T21	2		T40	18
values[3]	593	1			T15	4		T16	1		T20	1
values[4]	769	1			T8	5		T14	8		T40	28
values[5]	665	1			T20	1		T129	19		T200	9
values[6]	573	1			T20	1		T41	1		T148	1
values[7]	575	1			T65	1		T126	18		T217	20
values[8]	611	1			T17	15		T102	17		T161	1
values[9]	784	1			T13	4		T22	6		T49	10
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T18	1		T130	2		T30	1
values[1]	2647	1			T19	8		T21	2		T40	18
values[2]	628	1			T15	4		T16	1		T20	1
values[3]	748	1			T8	5		T14	8		T49	33
values[4]	602	1			T20	1		T65	24		T243	4
values[5]	648	1			T20	1		T41	1		T148	1
values[6]	579	1			T65	1		T217	20		T215	7
values[7]	521	1			T13	4		T17	15		T49	2
values[8]	865	1			T22	6		T128	19		T65	2
values[9]	116	1			T49	8		T100	1		T203	8
minimum	14333	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T18	1		T130	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T130	1		T127	14		T98	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T19	1		T21	1		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T200	8		T150	16		T244	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	4		T16	1		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	13		T131	1		T206	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	4		T14	6		T49	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T129	19		T200	9		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T243	4		T95	1		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	1		T65	11		T101	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T148	1		T139	13		T133	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T20	1		T41	1		T126	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T217	11		T225	7		T188	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T65	1		T215	1		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T102	8		T161	1		T135	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T17	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T95	1		T100	9		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T22	4		T128	9		T65	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T49	6		T100	1		T254	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T203	8		T139	11		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14043	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T163	15		T255	1		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T142	2		T230	7		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T127	19		T98	13		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	864	1			T19	7		T21	1		T40	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T150	16		T244	1		T246	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T127	6		T152	10		T86	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T40	15		T142	2		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	1		T14	2		T49	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T207	6		T140	4		T223	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T95	10		T47	1		T208	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T65	13		T101	11		T208	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	11		T133	10		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T126	8		T102	7		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T217	9		T225	4		T188	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T215	6		T140	11		T188	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T102	9		T135	3		T230	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	1		T17	14		T49	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T95	13		T132	3		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	2		T128	10		T65	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T49	2		T249	2		T258	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T139	9		T223	4		T181	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T256	12		T259	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T100	1		T233	15		T153	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T65	1		T224	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T18	1		T130	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T130	1		T127	14		T204	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T19	1		T21	1		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T200	8		T98	1		T235	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	4		T16	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T131	1		T150	16		T206	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	4		T14	6		T49	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T40	13		T31	3		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T243	4		T95	1		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T20	1		T129	19		T200	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T148	1		T203	9		T139	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T20	1		T41	1		T65	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T217	11		T133	12		T188	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T65	1		T126	10		T140	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T102	8		T161	1		T225	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	1		T215	1		T204	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	6		T95	1		T100	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	3		T22	4		T49	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T153	10		T260	12		T249	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T65	1		T223	4		T245	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T102	8		T162	26		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T127	19		T245	9		T261	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T19	7		T21	1		T40	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T98	13		T244	1		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T127	6		T152	10		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T150	16		T142	2		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T14	2		T49	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	15		T140	4		T223	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T95	10		T47	1		T188	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T101	11		T207	6		T208	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T139	11		T227	1		T262	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T65	13		T102	7		T162	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T217	9		T133	10		T188	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T126	8		T140	11		T188	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T102	9		T225	4		T135	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T17	14		T215	6		T204	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T49	2		T95	13		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	1		T22	2		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	1		T130	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T130	1		T127	20		T98	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T19	8		T21	2		T40	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T200	1		T150	17		T244	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T15	4		T16	1		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	16		T131	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	4		T14	6		T49	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T129	1		T200	1		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T243	1		T95	11		T47	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T20	1		T65	14		T101	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T148	1		T139	12		T133	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T20	1		T41	1		T126	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T217	10		T225	5		T188	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T65	1		T215	7		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T102	10		T161	1		T135	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	3		T17	15		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T95	14		T100	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T22	5		T128	11		T65	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T49	3		T100	1		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T203	1		T139	11		T223	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14202	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T163	1		T255	1		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T100	8		T235	6		T142	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T127	13		T235	20		T204	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T40	8		T50	14		T51	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T200	7		T150	15		T244	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T127	6		T200	4		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	12		T206	21		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T14	2		T49	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T129	18		T200	8		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T243	3		T47	1		T203	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T65	10		T208	13		T254	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T139	12		T133	11		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T126	9		T102	10		T202	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T217	10		T225	6		T188	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T140	12		T232	11		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T102	7		T135	4		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	1		T204	21		T222	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T100	8		T132	9		T225	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T22	1		T128	8		T232	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T49	5		T254	7		T249	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T203	7		T139	9		T181	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T102	11		T162	24		T229	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T163	14		T256	12		T259	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T100	1		T233	1		T153	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T65	2		T224	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T18	1		T130	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	1		T127	20		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T19	8		T21	2		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T200	1		T98	14		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	4		T16	1		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T131	1		T150	17		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	4		T14	6		T49	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	16		T31	2		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T243	1		T95	11		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	1		T129	1		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T148	1		T203	1		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	1		T41	1		T65	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T217	10		T133	11		T188	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T65	1		T126	9		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T102	10		T161	1		T225	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	15		T215	7		T204	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T49	3		T95	14		T100	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	3		T22	5		T49	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T233	14		T153	9		T254	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T203	7		T263	9		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T100	8		T102	11		T235	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T127	13		T204	2		T163	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T40	8		T50	14		T51	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T200	7		T235	20		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T129	18		T127	6		T200	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	15		T206	21		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T14	2		T49	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	12		T31	1		T223	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T243	3		T47	1		T188	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T129	18		T200	8		T208	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T203	8		T139	12		T155	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T65	10		T102	10		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T217	10		T133	11		T188	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T126	9		T140	12		T254	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T102	7		T225	6		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T204	21		T232	11		T239	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	5		T100	8		T132	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	1		T22	1		T128	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2