Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19261

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3063

1

T14

8

T15

4

T18

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16930

1

T1

20

T4

15

T5

20

auto[1]

5394

1

T14

8

T15

4

T17

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T264	3		-	-		-	-
values[0]	35	1			T183	1		T185	19		T265	14
values[1]	606	1			T18	1		T20	1		T40	18
values[2]	547	1			T20	1		T243	4		T102	18
values[3]	733	1			T17	15		T41	1		T65	1
values[4]	852	1			T21	2		T129	38		T30	1
values[5]	2721	1			T19	8		T50	15		T151	8
values[6]	624	1			T129	13		T127	33		T31	3
values[7]	449	1			T8	5		T13	4		T20	1
values[8]	673	1			T49	2		T148	1		T100	1
values[9]	980	1			T14	8		T15	4		T16	1
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	754	1			T18	1		T65	24		T126	18
values[1]	576	1			T20	1		T40	18		T130	1
values[2]	769	1			T17	15		T20	1		T41	1
values[3]	2862	1			T19	8		T21	2		T50	15
values[4]	670	1			T127	33		T100	9		T102	20
values[5]	568	1			T20	1		T31	3		T235	21
values[6]	431	1			T13	4		T148	1		T65	2
values[7]	727	1			T8	5		T49	2		T101	12
values[8]	734	1			T14	8		T15	4		T16	1
values[9]	124	1			T40	28		T266	3		T153	24
minimum	14109	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T161	1		T132	10		T133	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T18	1		T65	11		T126	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T243	4		T102	11		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	1		T40	9		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T17	1		T20	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T129	19		T127	7		T98	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T19	1		T50	15		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T21	1		T130	1		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T127	14		T100	9		T102	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T161	1		T139	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T235	21		T135	5		T208	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T20	1		T31	3		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	3		T100	1		T206	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T148	1		T65	1		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	4		T225	7		T204	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T49	1		T101	1		T144	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T16	1		T49	24		T128	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	6		T15	4		T22	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T40	13		T266	1		T222	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T153	12		T267	1		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T203	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T132	3		T133	10		T162	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	13		T126	8		T95	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T102	7		T217	9		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	9		T47	1		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T17	14		T95	10		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T127	6		T98	13		T214	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	858	1			T19	7		T151	7		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T21	1		T188	9		T261	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T127	19		T102	8		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T139	11		T140	4		T86	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T135	3		T208	2		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T134	15		T230	9		T270	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T13	1		T139	1		T168	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T65	1		T102	9		T223	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T225	4		T204	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T49	1		T101	11		T271	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	17		T128	10		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	2		T22	2		T139	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T40	15		T266	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T153	12		T268	3		T220	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T183	1		T185	9		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T265	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T161	1		T132	10		T133	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	1		T20	1		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T20	1		T243	4		T102	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T152	14		T224	1		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T17	1		T41	1		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T130	1		T138	1		T127	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T129	19		T30	1		T150	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T21	1		T129	19		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T19	1		T50	15		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T130	1		T32	2		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	14		T225	14		T135	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T129	13		T31	3		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	4		T13	3		T206	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T20	1		T65	1		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T100	1		T225	7		T188	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	1		T148	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T16	1		T40	13		T49	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	6		T15	4		T22	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T264	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T185	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	3		T133	10		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T40	9		T65	13		T126	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T102	7		T188	13		T186	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T152	10		T47	1		T244	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T17	14		T95	10		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	6		T214	16		T185	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T150	16		T215	6		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T21	1		T98	13		T188	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	885	1			T19	7		T151	7		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T139	11		T210	8		T272	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T127	19		T225	11		T135	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T140	4		T134	15		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T8	1		T13	1		T139	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T65	1		T102	9		T223	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	4		T188	8		T213	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T101	11		T139	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T40	15		T49	17		T128	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	2		T22	2		T223	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T161	1		T132	4		T133	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	1		T65	14		T126	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T243	1		T102	8		T217	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T20	1		T40	10		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T17	15		T20	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T129	1		T127	7		T98	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T19	8		T50	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T21	2		T130	1		T32	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T127	20		T100	1		T102	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T161	1		T139	12		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T235	1		T135	4		T208	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T20	1		T31	2		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	3		T100	1		T206	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T148	1		T65	2		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	4		T225	5		T204	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T49	2		T101	12		T144	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T16	1		T49	19		T128	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	6		T15	4		T22	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T40	16		T266	3		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T153	13		T267	1		T268	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T203	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T132	9		T133	11		T162	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T65	10		T126	9		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T243	3		T102	10		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	8		T47	1		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T129	18		T200	7		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T129	18		T127	6		T204	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T50	14		T51	6		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T213	7		T231	5		T261	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T127	13		T100	8		T102	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T139	12		T232	11		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T235	20		T135	4		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	1		T134	16		T230	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T13	1		T206	21		T69	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T129	12		T102	7		T223	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T225	6		T204	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T271	9		T251	7		T222	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	22		T128	8		T126	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T14	2		T22	1		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T40	12		T222	17		T273	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T153	11		T220	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T203	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T264	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T183	1		T185	11		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T161	1		T132	4		T133	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T18	1		T20	1		T40	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T20	1		T243	1		T102	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T152	11		T224	1		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T17	15		T41	1		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T130	1		T138	1		T127	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	1		T30	1		T150	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T21	2		T129	1		T98	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T19	8		T50	1		T151	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T130	1		T32	2		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T127	20		T225	12		T135	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T129	1		T31	2		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T8	4		T13	3		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T20	1		T65	2		T102	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T100	1		T225	5		T188	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T49	2		T148	1		T101	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T16	1		T40	16		T49	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	6		T15	4		T22	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T185	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T265	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	9		T133	11		T162	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	8		T65	10		T126	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T243	3		T102	10		T188	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	13		T47	1		T244	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T200	7		T217	10		T162	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	6		T204	2		T214	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	18		T150	15		T202	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T129	18		T213	7		T233	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T50	14		T51	6		T253	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T139	12		T231	5		T210	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T127	13		T225	13		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T129	12		T31	1		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	1		T13	1		T206	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T102	7		T223	5		T274	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	6		T188	10		T213	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	9		T275	9		T271	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T40	12		T49	22		T128	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	2		T22	1		T230	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2