Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19248

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3076

1

T8

5

T13

4

T15

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16505

1

T1

20

T4

15

T5

20

auto[1]

5819

1

T8

5

T13

4

T14

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	663	1			T15	2		T46	1		T65	2
values[0]	14	1			T283	13		T285	1		-	-
values[1]	558	1			T40	18		T49	33		T31	3
values[2]	2730	1			T17	15		T19	8		T20	1
values[3]	538	1			T49	2		T130	1		T101	12
values[4]	663	1			T13	4		T16	1		T22	6
values[5]	624	1			T20	1		T21	2		T30	1
values[6]	611	1			T14	8		T20	1		T200	8
values[7]	616	1			T15	4		T41	1		T49	8
values[8]	650	1			T8	5		T200	9		T95	11
values[9]	928	1			T18	1		T148	1		T65	25
minimum	13729	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	548	1			T17	15		T20	1		T31	3
values[1]	2632	1			T19	8		T50	15		T151	8
values[2]	520	1			T49	2		T129	19		T101	12
values[3]	748	1			T13	4		T16	1		T22	6
values[4]	572	1			T14	8		T20	2		T21	2
values[5]	635	1			T15	4		T200	8		T98	1
values[6]	616	1			T8	5		T41	1		T49	8
values[7]	717	1			T65	1		T129	13		T138	1
values[8]	915	1			T148	1		T65	26		T130	1
values[9]	93	1			T18	1		T127	13		T206	5
minimum	14328	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	1		T20	1		T95	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	3		T95	1		T140	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T19	1		T50	15		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T126	10		T200	5		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	1		T129	19		T212	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T101	1		T211	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T16	1		T129	19		T235	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	3		T22	4		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	6		T20	1		T127	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T20	1		T21	1		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T200	8		T207	1		T150	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	4		T98	1		T102	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T41	1		T100	9		T217	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	4		T49	6		T95	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T65	1		T200	9		T152	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T129	13		T138	1		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T65	11		T202	1		T203	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T148	1		T65	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T18	1		T206	5		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T127	7		T286	1		T287	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14032	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T40	9		T49	18		T161	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T17	14		T95	4		T225	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T95	13		T140	11		T268	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	876	1			T19	7		T151	7		T128	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T126	9		T229	12		T251	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T49	1		T212	4		T288	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T101	11		T211	8		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T188	8		T230	21		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T22	2		T40	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	2		T127	19		T102	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T21	1		T188	9		T162	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T207	6		T150	16		T208	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T102	7		T208	16		T271	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T217	9		T223	4		T244	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	1		T49	2		T95	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T152	10		T132	1		T215	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	3		T209	9		T226	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	13		T133	10		T266	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T65	1		T102	8		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T245	9		T153	12		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T127	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T40	9		T49	15		T283	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	455	1			T15	2		T46	1		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T65	1		T127	7		T32	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T283	1		T285	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T95	1		T217	1		T204	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	9		T49	18		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1514	1			T17	1		T19	1		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T126	10		T200	5		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	1		T130	1		T239	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T101	1		T211	1		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T16	1		T129	38		T235	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	3		T22	4		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	1		T127	14		T235	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T21	1		T30	1		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	6		T200	8		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	1		T208	14		T233	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	1		T100	9		T217	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	4		T49	6		T98	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T200	9		T152	14		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T95	1		T132	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T18	1		T65	12		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T148	1		T129	13		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13593	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T245	9		T289	12		T241	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T65	1		T127	6		T290	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T283	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T95	4		T214	16		T230	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T40	9		T49	15		T95	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T17	14		T19	7		T151	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T126	9		T140	11		T251	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T49	1		T239	13		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T101	11		T211	8		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T188	8		T230	21		T257	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	1		T22	2		T40	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T127	19		T204	16		T186	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T21	1		T188	9		T162	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	2		T102	9		T207	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T208	16		T251	10		T86	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T217	9		T244	1		T164	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T49	2		T98	13		T102	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T152	10		T132	1		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T95	10		T132	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T65	13		T215	6		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T102	8		T139	9		T225	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T17	15		T20	1		T95	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	2		T95	14		T140	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T19	8		T50	1		T151	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T126	10		T200	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T49	2		T129	1		T212	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T101	12		T211	9		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T16	1		T129	1		T235	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T22	5		T40	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	6		T20	1		T127	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T20	1		T21	2		T188	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T200	1		T207	7		T150	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	4		T98	1		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T41	1		T100	1		T217	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T8	4		T49	3		T95	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T65	1		T200	1		T152	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T129	1		T138	1		T132	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T65	14		T202	1		T203	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T148	1		T65	2		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T18	1		T206	1		T245	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T127	7		T286	1		T287	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14154	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T40	10		T49	16		T161	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T225	6		T214	17		T229	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T31	1		T140	12		T143	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T50	14		T51	6		T128	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T126	9		T200	4		T229	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T129	18		T212	3		T291	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T229	10		T231	8		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T129	18		T235	6		T188	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	1		T22	1		T40	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	2		T127	13		T102	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T162	3		T180	12		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T200	7		T150	15		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T102	10		T208	13		T233	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T100	8		T217	10		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T49	5		T47	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T200	8		T152	13		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T129	12		T132	9		T206	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T65	10		T203	15		T133	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T243	3		T100	8		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T206	4		T153	11		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T127	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T204	2		T230	9		T272	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T40	8		T49	17		T227	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	446	1			T15	2		T46	1		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T65	2		T127	7		T32	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T283	13		T285	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T95	5		T217	1		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T40	10		T49	16		T31	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T17	15		T19	8		T20	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T126	10		T200	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T49	2		T130	1		T239	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T101	12		T211	9		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	1		T129	2		T235	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	3		T22	5		T40	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	1		T127	20		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T21	2		T30	1		T188	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	6		T200	1		T102	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T208	17		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T41	1		T100	1		T217	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	4		T49	3		T98	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T200	1		T152	11		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	4		T95	11		T132	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T18	1		T65	15		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T148	1		T129	1		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13729	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T206	4		T203	7		T289	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T127	6		T290	16		T265	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T204	2		T214	17		T230	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T40	8		T49	17		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T50	14		T51	6		T128	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T126	9		T200	4		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T239	5		T212	3		T164	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T229	24		T231	8		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T129	36		T235	6		T188	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T13	1		T22	1		T40	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T127	13		T235	20		T204	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T162	3		T180	12		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	2		T200	7		T102	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T208	13		T233	14		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T100	8		T217	10		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	5		T102	10		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T200	8		T152	13		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	1		T132	9		T206	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T65	10		T203	8		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T129	12		T243	3		T100	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2