Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19114

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3210

1

T14

8

T15

4

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16855

1

T1

20

T4

15

T5

20

auto[1]

5469

1

T16

1

T18

1

T19

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	66	1			T229	23		T292	11		T242	32
values[0]	102	1			T20	1		T100	1		T139	24
values[1]	725	1			T22	6		T65	2		T130	2
values[2]	556	1			T13	4		T14	8		T41	1
values[3]	669	1			T148	1		T128	19		T31	3
values[4]	684	1			T127	33		T200	5		T95	11
values[5]	2541	1			T16	1		T18	1		T19	8
values[6]	656	1			T17	15		T20	1		T40	28
values[7]	666	1			T40	18		T49	8		T65	24
values[8]	660	1			T20	1		T49	33		T200	8
values[9]	898	1			T8	5		T15	4		T21	2
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	927	1			T14	8		T20	1		T22	6
values[1]	617	1			T13	4		T41	1		T148	1
values[2]	686	1			T128	19		T127	33		T31	3
values[3]	2738	1			T19	8		T50	15		T151	8
values[4]	451	1			T16	1		T18	1		T40	28
values[5]	677	1			T17	15		T20	1		T129	32
values[6]	574	1			T40	18		T49	8		T65	24
values[7]	615	1			T20	1		T49	33		T200	8
values[8]	747	1			T15	4		T21	2		T65	1
values[9]	161	1			T8	5		T32	2		T281	1
minimum	14131	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T130	2		T138	1		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T14	6		T20	1		T22	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T13	3		T202	10		T132	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	1		T148	1		T235	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	3		T95	1		T206	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T128	9		T127	14		T101	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T19	1		T50	15		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T135	5		T141	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T18	1		T288	1		T163	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	1		T40	13		T200	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T20	1		T129	19		T243	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	1		T129	13		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T40	9		T49	6		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T65	11		T149	1		T140	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	18		T47	5		T142	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T20	1		T200	8		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T21	1		T126	10		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	4		T65	1		T200	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T8	4		T32	2		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T154	1		T293	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13971	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T222	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T132	1		T215	6		T139	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	2		T22	2		T49	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T132	3		T225	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T133	10		T204	16		T251	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T95	4		T210	11		T295	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T128	10		T127	19		T101	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	868	1			T19	7		T151	7		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T135	3		T266	2		T154	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T288	10		T168	3		T296	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T40	15		T95	10		T102	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T223	4		T208	2		T142	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	14		T126	8		T207	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T40	9		T49	2		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T65	13		T140	11		T244	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	15		T47	1		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T230	12		T245	5		T297	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T21	1		T126	9		T127	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T98	13		T188	21		T185	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T8	1		T134	15		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T154	15		T237	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T14	2		T15	5		T22	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T229	11		T292	11		T242	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T100	1		T282	2		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T20	1		T139	13		T251	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T130	2		T138	1		T132	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	4		T65	1		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	3		T132	10		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	6		T41	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T31	3		T95	1		T202	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T148	1		T128	9		T101	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T206	22		T225	7		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	14		T200	5		T95	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T18	1		T19	1		T50	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T16	1		T131	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	1		T129	19		T243	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	1		T40	13		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	9		T49	6		T203	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T65	11		T149	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	18		T217	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T20	1		T200	8		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T8	4		T21	1		T126	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	4		T65	1		T200	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T229	12		T242	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T298	11		T299	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T139	11		T251	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T132	1		T215	6		T162	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	2		T65	1		T152	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T132	3		T139	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	2		T49	1		T133	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T95	4		T87	11		T295	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T128	10		T101	11		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T225	4		T188	9		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T127	19		T95	10		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	825	1			T19	7		T151	7		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T135	3		T296	13		T300	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T223	4		T288	10		T227	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T17	14		T40	15		T126	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T40	9		T49	2		T208	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T65	13		T207	6		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T49	15		T47	1		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T208	16		T245	5		T167	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T21	1		T126	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T98	13		T188	21		T185	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T130	2		T138	1		T100	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T14	6		T20	1		T22	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	3		T202	1		T132	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T41	1		T148	1		T235	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T31	2		T95	5		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T128	11		T127	20		T101	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T19	8		T50	1		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T135	4		T141	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	1		T288	11		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T16	1		T40	16		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T20	1		T129	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T17	15		T129	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	10		T49	3		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T65	14		T149	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	16		T47	5		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T20	1		T200	1		T98	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T21	2		T126	10		T127	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	4		T65	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T8	4		T32	2		T281	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T154	16		T293	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14111	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T222	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T132	12		T162	11		T214	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	2		T22	1		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T202	9		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T235	20		T133	11		T204	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T31	1		T206	21		T204	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T128	8		T127	13		T216	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T50	14		T51	6		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T135	4		T222	17		T254	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T163	9		T254	7		T260	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T40	12		T200	4		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	18		T243	3		T203	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T129	12		T126	9		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	8		T49	5		T180	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T65	10		T140	12		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	17		T47	1		T142	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T200	7		T235	6		T203	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T126	9		T127	6		T100	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T200	8		T100	8		T188	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T8	1		T134	16		T275	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T237	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T222	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T229	13		T292	1		T242	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T100	1		T282	2		T298	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T20	1		T139	12		T251	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T130	2		T138	1		T132	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T22	5		T65	2		T152	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	3		T132	4		T139	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	6		T41	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T31	2		T95	5		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T148	1		T128	11		T101	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T206	1		T225	5		T188	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T127	20		T200	1		T95	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T18	1		T19	8		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T16	1		T131	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T20	1		T129	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	15		T40	16		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T40	10		T49	3		T203	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T65	14		T149	1		T207	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	16		T217	1		T47	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	1		T200	1		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T8	4		T21	2		T126	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T15	4		T65	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T229	10		T292	10		T242	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T299	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T139	12		T251	7		T302	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T132	12		T162	11		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T22	1		T152	13		T217	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	1		T132	9		T225	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	2		T235	20		T133	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	1		T202	9		T204	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T128	8		T204	21		T216	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T206	21		T225	6		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T127	13		T200	4		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1178	1			T50	14		T51	6		T253	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T135	4		T231	8		T222	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T129	18		T243	3		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	12		T129	12		T126	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	8		T49	5		T203	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T65	10		T162	13		T232	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	17		T47	1		T142	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T200	7		T235	6		T203	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	1		T126	9		T127	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T200	8		T100	8		T188	25

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2