Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18939

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3385

1

T13

4

T15

4

T20

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17050

1

T1

20

T4

15

T5

20

auto[1]

5274

1

T13

4

T14

8

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T188	19		T288	11		T246	7
values[0]	10	1			T130	1		T30	1		T254	8
values[1]	407	1			T15	4		T22	6		T65	2
values[2]	639	1			T20	1		T127	13		T95	16
values[3]	627	1			T14	8		T18	1		T243	4
values[4]	556	1			T8	5		T21	2		T65	1
values[5]	641	1			T13	4		T41	1		T126	19
values[6]	441	1			T126	18		T31	3		T202	10
values[7]	755	1			T20	1		T148	1		T128	19
values[8]	2824	1			T19	8		T49	10		T50	15
values[9]	1282	1			T16	1		T17	15		T20	1
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	604	1			T15	4		T22	6		T65	2
values[1]	572	1			T95	11		T152	24		T149	1
values[2]	562	1			T14	8		T18	1		T20	1
values[3]	633	1			T8	5		T13	4		T21	2
values[4]	611	1			T41	1		T126	37		T149	1
values[5]	488	1			T128	19		T65	24		T138	1
values[6]	2827	1			T19	8		T20	1		T49	8
values[7]	808	1			T20	1		T49	2		T129	19
values[8]	933	1			T16	1		T17	15		T40	46
values[9]	168	1			T207	7		T47	6		T188	19
minimum	14118	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T22	4		T65	1		T129	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	4		T30	1		T127	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T95	1		T152	14		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T149	1		T150	16		T223	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	6		T18	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T20	1		T243	4		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	4		T21	1		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	3		T149	1		T206	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T224	1		T132	13		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T41	1		T126	20		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T65	11		T138	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T128	9		T31	3		T102	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T19	1		T50	15		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T20	1		T49	6		T235	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T134	17		T244	4		T216	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T20	1		T49	1		T129	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T16	1		T17	1		T40	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T40	9		T49	18		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T47	5		T288	1		T234	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T207	1		T188	11		T275	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13966	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T22	2		T65	1		T95	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T127	6		T211	8		T223	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T95	10		T152	10		T215	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T150	16		T223	5		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T14	2		T139	11		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T95	13		T162	15		T87	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	1		T21	1		T98	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	1		T162	2		T229	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T132	1		T239	13		T186	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T126	17		T204	16		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T65	13		T132	3		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T128	10		T102	7		T135	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	842	1			T19	7		T151	7		T127	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T49	2		T140	4		T188	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T134	15		T244	1		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	1		T229	24		T212	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	14		T40	15		T208	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	9		T49	15		T139	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T47	1		T288	10		T296	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T207	6		T188	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	2		T15	5		T22	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T245	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T288	1		T246	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T188	11		T303	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T130	1		T254	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T22	4		T65	1		T129	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T15	4		T131	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T95	2		T217	1		T232	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T20	1		T127	7		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	6		T18	1		T152	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T243	4		T95	1		T162	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	4		T21	1		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T149	1		T206	5		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T98	1		T224	1		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	3		T41	1		T126	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T161	1		T34	5		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T126	10		T31	3		T202	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T148	1		T65	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T20	1		T128	9		T102	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T19	1		T50	15		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T49	7		T129	19		T200	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T16	1		T17	1		T40	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T20	1		T40	9		T49	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T288	10		T246	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	8		T303	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T22	2		T65	1		T102	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T211	8		T183	3		T230	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T95	14		T185	11		T153	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T127	6		T150	16		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	2		T152	10		T215	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T95	13		T162	15		T214	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T21	1		T217	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T229	7		T227	1		T87	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T98	13		T132	1		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	1		T126	9		T204	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T208	2		T153	10		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T126	8		T135	3		T304	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	13		T127	19		T101	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T128	10		T102	7		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T19	7		T151	7		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	3		T162	11		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T17	14		T40	15		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T40	9		T49	15		T207	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	5		T65	2		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	4		T30	1		T127	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T95	11		T152	11		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	1		T150	17		T223	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	6		T18	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T20	1		T243	1		T95	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	4		T21	2		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	3		T149	1		T206	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T224	1		T132	2		T281	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T41	1		T126	19		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	14		T138	1		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	11		T31	2		T102	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T19	8		T50	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T20	1		T49	3		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T134	16		T244	3		T216	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T20	1		T49	2		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T17	15		T40	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T40	10		T49	16		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T47	5		T288	11		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T207	7		T188	9		T275	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14112	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T245	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T22	1		T129	18		T200	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	6		T230	9		T251	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	13		T232	1		T222	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T150	15		T223	5		T214	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T14	2		T139	12		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T243	3		T162	11		T143	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	1		T129	12		T100	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	1		T206	4		T162	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T132	12		T239	5		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T126	18		T202	9		T203	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T65	10		T132	9		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T128	8		T31	1		T102	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T50	14		T51	6		T253	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T49	5		T235	20		T206	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T134	16		T244	2		T216	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T129	18		T200	7		T229	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	12		T200	8		T208	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T40	8		T49	17		T235	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T47	1		T234	11		T305	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T188	10		T275	9		T306	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T288	11		T246	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T188	9		T303	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T130	1		T254	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T22	5		T65	2		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	4		T131	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T95	16		T217	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T20	1		T127	7		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T14	6		T18	1		T152	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T243	1		T95	14		T162	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	4		T21	2		T65	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T149	1		T206	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T98	14		T224	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	3		T41	1		T126	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T161	1		T34	5		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T126	9		T31	2		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T148	1		T65	14		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T128	11		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T19	8		T50	1		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T49	5		T129	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T16	1		T17	15		T40	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T20	1		T40	10		T49	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T246	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T188	10		T303	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T254	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T22	1		T129	18		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T230	9		T251	11		T86	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T232	1		T185	13		T143	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	6		T150	15		T223	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T14	2		T152	13		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T243	3		T162	11		T214	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	1		T129	12		T100	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T206	4		T143	14		T229	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T132	12		T239	5		T231	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T126	9		T203	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T208	2		T153	9		T307	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T126	9		T31	1		T202	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T65	10		T127	13		T102	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T128	8		T102	10		T235	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T50	14		T51	6		T253	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T49	5		T129	18		T200	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T40	12		T200	8		T47	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T40	8		T49	17		T235	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2