Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22324

1

T1

20

T4

15

T5

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

18896

1

T1

20

T4

15

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3428

1

T13

4

T15

4

T20

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17035

1

T1

20

T4

15

T5

20

auto[1]

5289

1

T13

4

T14

8

T15

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18852

1

T1

20

T4

15

T5

20

auto[1]

3472

1

T8

1

T13

1

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	260	1			T40	18		T235	7		T47	6
values[0]	20	1			T30	1		T308	19		-	-
values[1]	414	1			T15	4		T22	6		T65	2
values[2]	702	1			T20	1		T127	13		T95	16
values[3]	482	1			T14	8		T18	1		T243	4
values[4]	635	1			T8	5		T65	1		T129	13
values[5]	544	1			T13	4		T21	2		T41	1
values[6]	594	1			T65	24		T126	37		T31	3
values[7]	724	1			T20	1		T148	1		T128	19
values[8]	2701	1			T19	8		T49	10		T50	15
values[9]	1147	1			T16	1		T17	15		T20	1
minimum	14101	1			T1	20		T4	15		T5	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	437	1			T15	4		T65	2		T129	19
values[1]	614	1			T95	16		T152	24		T149	1
values[2]	542	1			T14	8		T18	1		T20	1
values[3]	610	1			T8	5		T13	4		T21	2
values[4]	612	1			T41	1		T126	37		T149	1
values[5]	547	1			T128	19		T65	24		T138	1
values[6]	2759	1			T19	8		T20	1		T49	8
values[7]	850	1			T20	1		T49	2		T129	19
values[8]	965	1			T16	1		T17	15		T40	46
values[9]	116	1			T200	9		T234	12		T305	10
minimum	14272	1			T1	20		T4	15		T5	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

3949

1

T8

1

T13

1

T14

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T65	1		T129	19		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	4		T127	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T95	2		T152	14		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T149	1		T150	16		T223	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T14	6		T18	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T20	1		T243	4		T95	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	4		T21	1		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	3		T149	1		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T224	1		T281	1		T34	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T41	1		T126	20		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T128	9		T65	11		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T31	3		T102	11		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T19	1		T50	15		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T20	1		T49	6		T235	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T244	4		T216	3		T233	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T20	1		T49	1		T129	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T16	1		T17	1		T40	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T40	9		T49	18		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T200	9		T234	12		T305	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14001	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T30	1		T211	1		T183	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T65	1		T102	9		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T127	6		T223	4		T261	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T95	14		T152	10		T215	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T150	16		T223	5		T214	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T14	2		T139	11		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T95	13		T162	15		T87	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	1		T21	1		T98	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T217	9		T162	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T239	13		T186	1		T154	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T126	17		T204	16		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T128	10		T65	13		T132	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T102	7		T140	4		T135	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	828	1			T19	7		T151	7		T127	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	2		T188	22		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T244	1		T216	9		T205	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T49	1		T229	24		T212	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	14		T40	15		T47	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T40	9		T49	15		T207	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T296	13		T310	5		T237	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	2		T15	5		T22	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T211	8		T183	3		T230	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T47	5		T208	14		T266	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T40	9		T235	7		T213	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T308	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T22	4		T65	1		T129	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T15	4		T131	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T95	2		T217	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T20	1		T127	7		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	6		T18	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T243	4		T95	1		T162	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	4		T65	1		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T217	11		T206	5		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T21	1		T224	1		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	3		T41	1		T149	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T65	11		T161	1		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T126	20		T31	3		T102	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T148	1		T128	9		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T20	1		T235	21		T206	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T19	1		T50	15		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T49	7		T129	19		T200	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T16	1		T17	1		T40	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T20	1		T49	18		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13965	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T47	1		T208	16		T266	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T40	9		T168	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T308	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T22	2		T65	1		T102	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T211	8		T183	3		T230	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T95	14		T215	6		T185	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	6		T150	16		T223	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T14	2		T152	10		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T95	13		T162	15		T87	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T98	13		T245	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T217	9		T229	7		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T21	1		T132	1		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	1		T162	2		T213	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T65	13		T208	2		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T126	17		T102	7		T204	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T128	10		T127	19		T101	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T140	4		T188	22		T230	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	841	1			T19	7		T151	7		T269	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T49	3		T162	11		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T17	14		T40	15		T134	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T49	15		T207	6		T139	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T15	5		T22	9

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T65	2		T129	1		T130	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T15	4		T127	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T95	16		T152	11		T217	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	1		T150	17		T223	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	6		T18	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	1		T243	1		T95	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	4		T21	2		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	3		T149	1		T217	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T224	1		T281	1		T34	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T41	1		T126	19		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T128	11		T65	14		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	2		T102	8		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T19	8		T50	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	1		T49	3		T235	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T244	3		T216	10		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T20	1		T49	2		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T16	1		T17	15		T40	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T40	10		T49	16		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T200	1		T234	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14161	1			T1	20		T4	15		T5	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T30	1		T211	9		T183	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T129	18		T200	4		T100	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T127	6		T261	2		T178	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T152	13		T232	1		T185	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T150	15		T223	5		T214	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	2		T139	12		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T243	3		T162	11		T143	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	1		T129	12		T100	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T217	10		T206	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T239	5		T231	8		T307	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T126	18		T202	9		T203	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T128	8		T65	10		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T31	1		T102	10		T135	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T50	14		T51	6		T253	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T49	5		T235	20		T206	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T244	2		T216	2		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T129	18		T200	7		T229	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	12		T47	1		T134	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T40	8		T49	17		T235	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T200	8		T234	11		T305	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T22	1		T308	12		T311	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T230	9		T251	11		T86	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	5		T208	17		T266	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T40	10		T235	1		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T308	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T30	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T22	5		T65	2		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	4		T131	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T95	16		T217	1		T215	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T20	1		T127	7		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T14	6		T18	1		T100	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T243	1		T95	14		T162	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	4		T65	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T217	10		T206	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T21	2		T224	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	3		T41	1		T149	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T65	14		T161	1		T208	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T126	19		T31	2		T102	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	1		T128	11		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	1		T235	1		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T19	8		T50	1		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	5		T129	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T16	1		T17	15		T40	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T20	1		T49	16		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14101	1			T1	20		T4	15		T5	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T47	1		T208	13		T246	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T40	8		T235	6		T213	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T308	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T22	1		T129	18		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T230	9		T251	11		T86	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T232	1		T185	13		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T127	6		T150	15		T223	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T14	2		T152	13		T139	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T243	3		T162	11		T87	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T129	12		T100	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T217	10		T206	4		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T132	12		T239	5		T231	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T203	8		T162	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T65	10		T208	2		T307	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T126	18		T31	1		T102	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T128	8		T127	13		T102	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T235	20		T206	21		T188	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T50	14		T51	6		T253	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	5		T129	18		T200	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	12		T200	8		T134	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T49	17		T225	6		T204	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18375

1

T1

20

T4

15

T5

20

auto[1]

auto[0]

3949

1

T8

1

T13

1

T14

2