Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1117218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1095616

1

T1

60

T2

2

T3

61

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1942720	1			T1	81		T2	1		T3	81
values[0x0]	134699	1			T1	33		T2	2		T3	29
values[0x1]	135415	1			T1	30		T2	4		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	893947	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1318887

1

T1

76

T2

4

T3

76

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6257	1			T10	4		T11	1		T12	5
valid_sources[0x01]	6674	1			T19	3		T6	1		T11	1
valid_sources[0x02]	7836	1			T1	5		T2	1		T4	1
valid_sources[0x03]	7714	1			T1	7		T6	2		T24	1
valid_sources[0x04]	12868	1			T10	1		T11	2		T24	1
valid_sources[0x05]	6605	1			T10	3		T24	1		T12	4
valid_sources[0x06]	11263	1			T6	2		T10	2		T11	1
valid_sources[0x07]	11672	1			T6	1		T10	1		T41	1
valid_sources[0x08]	10493	1			T6	3		T10	3		T11	1
valid_sources[0x09]	6689	1			T5	1		T6	2		T10	1
valid_sources[0x0a]	6696	1			T10	1		T24	1		T41	2
valid_sources[0x0b]	6593	1			T4	1		T6	2		T10	4
valid_sources[0x0c]	8005	1			T5	2		T10	2		T12	18
valid_sources[0x0d]	6760	1			T5	1		T10	2		T11	2
valid_sources[0x0e]	8080	1			T1	2		T6	1		T10	2
valid_sources[0x0f]	7089	1			T4	1		T12	9		T14	49
valid_sources[0x10]	6639	1			T6	2		T10	3		T11	3
valid_sources[0x11]	6848	1			T6	1		T10	2		T40	1
valid_sources[0x12]	8556	1			T6	1		T11	5		T24	1
valid_sources[0x13]	7986	1			T1	5		T9	1		T10	6
valid_sources[0x14]	6407	1			T1	6		T10	3		T11	1
valid_sources[0x15]	6904	1			T6	3		T10	6		T11	3
valid_sources[0x16]	7425	1			T9	1		T10	1		T11	1
valid_sources[0x17]	6835	1			T1	1		T10	3		T11	2
valid_sources[0x18]	6327	1			T4	1		T10	1		T24	3
valid_sources[0x19]	6808	1			T6	1		T10	2		T11	1
valid_sources[0x1a]	6745	1			T10	3		T11	3		T24	1
valid_sources[0x1b]	7467	1			T6	2		T10	3		T12	11
valid_sources[0x1c]	6050	1			T9	1		T10	6		T11	4
valid_sources[0x1d]	9178	1			T10	2		T11	2		T41	2
valid_sources[0x1e]	10607	1			T10	1		T11	3		T24	1
valid_sources[0x1f]	7531	1			T10	2		T11	1		T24	1
valid_sources[0x20]	6386	1			T6	1		T10	1		T11	2
valid_sources[0x21]	7276	1			T5	1		T6	1		T10	3
valid_sources[0x22]	6927	1			T1	5		T6	7		T10	2
valid_sources[0x23]	8211	1			T5	1		T10	1		T11	1
valid_sources[0x24]	7738	1			T20	1		T9	1		T10	6
valid_sources[0x25]	10934	1			T1	2		T4	4		T9	1
valid_sources[0x26]	7487	1			T10	5		T11	2		T12	22
valid_sources[0x27]	11854	1			T6	5		T10	1		T11	2
valid_sources[0x28]	6680	1			T2	1		T9	1		T10	2
valid_sources[0x29]	6752	1			T10	2		T11	3		T12	7
valid_sources[0x2a]	11144	1			T6	1		T21	1		T10	3
valid_sources[0x2b]	10716	1			T1	7		T12	6		T82	1
valid_sources[0x2c]	6524	1			T9	1		T10	1		T11	2
valid_sources[0x2d]	6659	1			T5	1		T6	2		T11	2
valid_sources[0x2e]	7177	1			T11	3		T40	1		T12	12
valid_sources[0x2f]	7453	1			T6	2		T9	1		T10	2
valid_sources[0x30]	16307	1			T6	1		T10	2		T12	14
valid_sources[0x31]	6550	1			T20	1		T10	2		T12	14
valid_sources[0x32]	8085	1			T5	1		T10	4		T24	1
valid_sources[0x33]	15258	1			T6	1		T10	5		T24	1
valid_sources[0x34]	6541	1			T22	1		T10	5		T24	2
valid_sources[0x35]	11151	1			T4	2		T6	1		T10	1
valid_sources[0x36]	6812	1			T10	1		T11	1		T12	6
valid_sources[0x37]	7974	1			T6	2		T10	3		T11	1
valid_sources[0x38]	6552	1			T6	1		T9	2		T10	9
valid_sources[0x39]	6663	1			T6	2		T10	1		T11	3
valid_sources[0x3a]	6477	1			T10	3		T12	16		T13	3
valid_sources[0x3b]	11219	1			T2	1		T6	2		T10	3
valid_sources[0x3c]	6979	1			T6	2		T21	1		T10	3
valid_sources[0x3d]	12519	1			T6	1		T10	1		T11	2
valid_sources[0x3e]	6698	1			T10	3		T24	1		T40	1
valid_sources[0x3f]	7992	1			T5	1		T6	1		T10	2
valid_sources[0x40]	6649	1			T3	144		T6	1		T10	2
valid_sources[0x41]	7698	1			T6	1		T9	1		T10	1
valid_sources[0x42]	6422	1			T6	1		T10	6		T24	1
valid_sources[0x43]	11050	1			T6	2		T10	1		T11	1
valid_sources[0x44]	10778	1			T6	4		T10	1		T11	1
valid_sources[0x45]	6519	1			T10	1		T11	2		T24	1
valid_sources[0x46]	6950	1			T1	8		T20	1		T6	4
valid_sources[0x47]	19099	1			T5	1		T6	1		T9	1
valid_sources[0x48]	6939	1			T10	2		T11	1		T41	2
valid_sources[0x49]	10771	1			T1	1		T6	1		T9	1
valid_sources[0x4a]	10849	1			T6	2		T10	2		T24	2
valid_sources[0x4b]	6558	1			T4	1		T10	2		T24	1
valid_sources[0x4c]	7842	1			T11	2		T24	1		T41	2
valid_sources[0x4d]	11171	1			T9	1		T10	2		T11	3
valid_sources[0x4e]	6866	1			T6	2		T10	1		T11	8
valid_sources[0x4f]	6714	1			T20	1		T6	2		T10	6
valid_sources[0x50]	10805	1			T6	3		T10	3		T11	3
valid_sources[0x51]	7048	1			T10	1		T11	1		T12	14
valid_sources[0x52]	8414	1			T10	2		T11	1		T40	4
valid_sources[0x53]	6770	1			T5	1		T11	4		T24	1
valid_sources[0x54]	7187	1			T5	1		T6	2		T10	3
valid_sources[0x55]	11817	1			T6	8		T10	3		T11	5
valid_sources[0x56]	6809	1			T6	1		T10	1		T11	1
valid_sources[0x57]	7530	1			T6	3		T10	4		T12	24
valid_sources[0x58]	6798	1			T6	1		T10	4		T11	1
valid_sources[0x59]	6669	1			T22	1		T10	2		T11	1
valid_sources[0x5a]	6838	1			T6	1		T9	1		T10	2
valid_sources[0x5b]	7412	1			T5	1		T6	1		T10	2
valid_sources[0x5c]	6685	1			T10	3		T11	3		T24	1
valid_sources[0x5d]	6641	1			T10	1		T24	1		T40	1
valid_sources[0x5e]	9465	1			T1	2		T9	1		T10	6
valid_sources[0x5f]	15070	1			T6	5		T10	4		T11	1
valid_sources[0x60]	12238	1			T2	1		T10	1		T24	1
valid_sources[0x61]	7316	1			T1	3		T6	1		T10	3
valid_sources[0x62]	10726	1			T10	4		T11	3		T24	2
valid_sources[0x63]	6754	1			T10	2		T11	1		T12	15
valid_sources[0x64]	6635	1			T1	2		T6	1		T11	2
valid_sources[0x65]	11859	1			T21	1		T10	2		T11	1
valid_sources[0x66]	15292	1			T5	1		T10	3		T11	2
valid_sources[0x67]	10941	1			T6	1		T7	144		T10	1
valid_sources[0x68]	6446	1			T10	1		T11	1		T24	1
valid_sources[0x69]	7412	1			T6	1		T10	3		T41	2
valid_sources[0x6a]	6782	1			T1	6		T11	1		T12	27
valid_sources[0x6b]	7595	1			T5	1		T9	2		T10	1
valid_sources[0x6c]	7005	1			T6	1		T10	2		T12	11
valid_sources[0x6d]	6359	1			T5	2		T10	1		T12	20
valid_sources[0x6e]	7866	1			T10	4		T11	3		T24	1
valid_sources[0x6f]	9270	1			T6	5		T10	3		T12	19
valid_sources[0x70]	6227	1			T10	3		T24	2		T40	1
valid_sources[0x71]	10843	1			T6	3		T10	2		T12	16
valid_sources[0x72]	10874	1			T10	4		T11	2		T12	15
valid_sources[0x73]	7176	1			T1	1		T5	2		T9	1
valid_sources[0x74]	7270	1			T4	1		T10	5		T11	2
valid_sources[0x75]	10940	1			T1	4		T6	8		T10	1
valid_sources[0x76]	6682	1			T10	2		T11	2		T12	11
valid_sources[0x77]	15154	1			T6	2		T9	1		T10	1
valid_sources[0x78]	7540	1			T10	2		T12	10		T14	2
valid_sources[0x79]	21945	1			T5	1		T11	1		T24	1
valid_sources[0x7a]	6583	1			T9	1		T10	3		T11	1
valid_sources[0x7b]	6634	1			T6	2		T10	2		T24	1
valid_sources[0x7c]	6477	1			T20	1		T9	1		T11	1
valid_sources[0x7d]	20460	1			T5	1		T9	1		T11	1
valid_sources[0x7e]	6812	1			T11	3		T24	1		T12	14
valid_sources[0x7f]	13886	1			T10	1		T11	1		T40	1
valid_sources[0x80]	7607	1			T11	5		T12	29		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

968786

1

T1

45

T3

43

T6

91

values[0x0]

all_enables

biggest_size

73756

1

T1

7

T2

2

T3

11

values[0x1]

all_enables

biggest_size

53074

1

T1

8

T3

7

T4

12