Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27090	1			T10	8		T12	10		T14	26
auto[PWRUP]	100	1			T48	1		T35	3		T349	1
auto[ONEST_0]	60	1			T47	2		T25	1		T49	1
auto[ONEST_021]	4	1			T55	2		T350	1		T351	1
auto[ONEST_1]	68	1			T47	1		T48	3		T49	2
auto[ONEST_DONE]	4	1			T48	1		T349	1		T352	1
auto[LP_0]	107	1			T47	3		T48	2		T49	1
auto[LP_021]	25	1			T47	1		T51	2		T55	1
auto[LP_1]	142	1			T47	2		T48	1		T35	2
auto[LP_EVAL]	62	1			T47	1		T48	2		T51	2
auto[LP_SLP]	442	1			T38	1		T47	8		T48	4
auto[LP_PWRUP]	31	1			T35	1		T51	1		T54	1
auto[NP_0]	142	1			T47	2		T48	1		T49	2
auto[NP_021]	34	1			T47	1		T35	1		T51	1
auto[NP_1]	142	1			T47	2		T48	4		T49	2
auto[NP_EVAL]	35	1			T47	2		T35	1		T51	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T353

1

T252

1

T354

1

min

26618

1

T10

8

T12

10

T14

26

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26622	1			T10	8		T12	10		T14	26
pow[0x1]	8	1			T349	1		T55	1		T355	1
pow[0x2]	10	1			T356	1		T357	2		T358	1
pow[0x3]	24	1			T48	1		T349	1		T54	1
pow[0x4]	65	1			T47	2		T48	1		T49	2
pow[0x5]	103	1			T47	3		T49	2		T35	2
pow[0x6]	219	1			T47	2		T48	4		T49	1
pow[0x7]	487	1			T47	6		T48	2		T49	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

173

1

T47

2

T49

1

T35

2

min

26166

1

T10

8

T12

10

T14

26

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26166	1			T10	8		T12	10		T14	26
pow[0x1]	1	1			T354	1		-	-		-	-
pow[0x3]	1	1			T359	1		-	-		-	-
pow[0x4]	1	1			T360	1		-	-		-	-
pow[0x6]	1	1			T356	1		-	-		-	-
pow[0x7]	3	1			T54	1		T52	1		T361	1
pow[0x8]	3	1			T54	1		T105	1		T362	1
pow[0x9]	6	1			T49	1		T35	1		T363	1
pow[0xa]	17	1			T349	1		T350	1		T364	1
pow[0xb]	43	1			T49	1		T35	2		T349	1
pow[0xc]	79	1			T48	1		T35	1		T51	1
pow[0xd]	137	1			T47	1		T48	3		T49	1
pow[0xe]	250	1			T38	1		T47	3		T48	5
pow[0xf]	528	1			T47	6		T48	7		T49	6