Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2093	1			T19	10		T6	7		T22	20
auto[PWRUP]	116	1			T43	1		T48	2		T49	1
auto[ONEST_0]	83	1			T10	1		T43	1		T47	1
auto[ONEST_021]	24	1			T54	1		T56	1		T350	1
auto[ONEST_1]	85	1			T36	1		T38	1		T39	1
auto[ONEST_DONE]	1	1			T365	1		-	-		-	-
auto[LP_0]	103	1			T13	1		T47	3		T49	2
auto[LP_021]	27	1			T48	1		T49	1		T35	1
auto[LP_1]	130	1			T6	1		T38	2		T47	2
auto[LP_EVAL]	40	1			T38	1		T43	1		T48	1
auto[LP_SLP]	468	1			T10	3		T11	1		T13	3
auto[LP_PWRUP]	30	1			T11	1		T47	2		T349	1
auto[NP_0]	172	1			T6	1		T36	1		T38	1
auto[NP_021]	48	1			T47	3		T35	4		T51	1
auto[NP_1]	169	1			T11	1		T38	1		T43	1
auto[NP_EVAL]	19	1			T10	1		T11	1		T38	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T349

2

T105

1

T362

1

min

1714

1

T19

10

T6

9

T22

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1726	1			T19	10		T6	9		T22	20
pow[0x1]	10	1			T349	1		T26	1		T366	1
pow[0x2]	11	1			T35	1		T366	1		T53	1
pow[0x3]	34	1			T47	1		T51	1		T55	1
pow[0x4]	57	1			T47	2		T48	1		T35	3
pow[0x5]	122	1			T13	1		T38	1		T47	4
pow[0x6]	249	1			T47	1		T48	3		T49	2
pow[0x7]	466	1			T47	9		T48	4		T49	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T38

1

T47

2

T48

4

min

1268

1

T19

10

T6

8

T22

20

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1272	1			T19	10		T6	8		T22	20
pow[0x1]	8	1			T195	1		T32	2		T205	2
pow[0x2]	5	1			T38	1		T25	1		T362	1
pow[0x3]	16	1			T11	1		T43	3		T201	1
pow[0x4]	15	1			T6	1		T11	1		T38	2
pow[0x5]	1	1			T49	1		-	-		-	-
pow[0x8]	9	1			T47	1		T355	1		T353	1
pow[0x9]	9	1			T49	1		T51	1		T367	1
pow[0xa]	17	1			T47	1		T35	1		T350	1
pow[0xb]	46	1			T49	1		T35	1		T51	2
pow[0xc]	63	1			T47	1		T49	2		T51	2
pow[0xd]	144	1			T47	4		T48	1		T49	2
pow[0xe]	242	1			T47	2		T48	1		T49	1
pow[0xf]	536	1			T38	3		T39	1		T47	13