Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	30579926	30508088	0	0
FsmStateHwReset_A	1005	1005	0	0
FsmStateSwReset_A	30579926	6350	0	0
LpSampleCntHwReset_A	1005	1005	0	0
LpSampleCntSwReset_A	30579926	6350	0	0
NpSampleCntHwReset_A	1005	1005	0	0
NpSampleCntSwReset_A	30579926	6350	0	0
PwrupTimerCntHwReset_A	1005	1005	0	0
PwrupTimerCntSwReset_A	30579926	6350	0	0
WakeupTimerCntHwReset_A	1005	1005	0	0
WakeupTimerCntSwReset_A	30579926	6350	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	30508088	0	0
T1	1148	1089	0	0
T2	81	1	0	0
T3	1149	1083	0	0
T4	670	576	0	0
T5	717	646	0	0
T6	916	600	0	0
T7	1156	1060	0	0
T8	6346	6263	0	0
T19	62	1	0	0
T20	93	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1005	1005	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	7	7	0	0
T7	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	6350	0	0
T12	38097	10	0	0
T13	74	0	0	0
T14	98248	26	0	0
T15	64993	19	0	0
T16	0	15	0	0
T17	0	6	0	0
T18	0	15	0	0
T34	0	22	0	0
T36	95	0	0	0
T37	0	7	0	0
T50	7449	0	0	0
T77	52	0	0	0
T78	66	0	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	1195	0	0	0
T83	755	0	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1005	1005	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	7	7	0	0
T7	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	6350	0	0
T12	38097	10	0	0
T13	74	0	0	0
T14	98248	26	0	0
T15	64993	19	0	0
T16	0	15	0	0
T17	0	6	0	0
T18	0	15	0	0
T34	0	22	0	0
T36	95	0	0	0
T37	0	7	0	0
T50	7449	0	0	0
T77	52	0	0	0
T78	66	0	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	1195	0	0	0
T83	755	0	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1005	1005	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	7	7	0	0
T7	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	6350	0	0
T12	38097	10	0	0
T13	74	0	0	0
T14	98248	26	0	0
T15	64993	19	0	0
T16	0	15	0	0
T17	0	6	0	0
T18	0	15	0	0
T34	0	22	0	0
T36	95	0	0	0
T37	0	7	0	0
T50	7449	0	0	0
T77	52	0	0	0
T78	66	0	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	1195	0	0	0
T83	755	0	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1005	1005	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	7	7	0	0
T7	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	6350	0	0
T12	38097	10	0	0
T13	74	0	0	0
T14	98248	26	0	0
T15	64993	19	0	0
T16	0	15	0	0
T17	0	6	0	0
T18	0	15	0	0
T34	0	22	0	0
T36	95	0	0	0
T37	0	7	0	0
T50	7449	0	0	0
T77	52	0	0	0
T78	66	0	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	1195	0	0	0
T83	755	0	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1005	1005	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	7	7	0	0
T7	1	1	0	0
T8	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30579926	6350	0	0
T12	38097	10	0	0
T13	74	0	0	0
T14	98248	26	0	0
T15	64993	19	0	0
T16	0	15	0	0
T17	0	6	0	0
T18	0	15	0	0
T34	0	22	0	0
T36	95	0	0	0
T37	0	7	0	0
T50	7449	0	0	0
T77	52	0	0	0
T78	66	0	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	1195	0	0	0
T83	755	0	0	0