Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
315619 |
0 |
0 |
| T1 |
552936 |
102 |
0 |
0 |
| T2 |
43874 |
0 |
0 |
0 |
| T3 |
127679 |
102 |
0 |
0 |
| T4 |
54392 |
54 |
0 |
0 |
| T5 |
712387 |
62 |
0 |
0 |
| T6 |
5349090 |
78 |
0 |
0 |
| T7 |
5648324 |
102 |
0 |
0 |
| T8 |
14959880 |
62 |
0 |
0 |
| T9 |
1466080 |
62 |
0 |
0 |
| T10 |
7218419 |
214 |
0 |
0 |
| T11 |
5707825 |
80 |
0 |
0 |
| T12 |
171441 |
34 |
0 |
0 |
| T13 |
0 |
38 |
0 |
0 |
| T14 |
0 |
102 |
0 |
0 |
| T15 |
0 |
68 |
0 |
0 |
| T16 |
0 |
68 |
0 |
0 |
| T17 |
0 |
34 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T19 |
367499 |
0 |
0 |
0 |
| T20 |
76311 |
0 |
0 |
0 |
| T21 |
422160 |
0 |
0 |
0 |
| T22 |
13204560 |
0 |
0 |
0 |
| T23 |
6972753 |
0 |
0 |
0 |
| T24 |
9301031 |
20 |
0 |
0 |
| T36 |
0 |
32 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T40 |
766469 |
0 |
0 |
0 |
| T41 |
117799 |
10 |
0 |
0 |
| T42 |
35137 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
317383 |
0 |
0 |
| T1 |
278190 |
102 |
0 |
0 |
| T2 |
22066 |
0 |
0 |
0 |
| T3 |
65563 |
102 |
0 |
0 |
| T4 |
28201 |
54 |
0 |
0 |
| T5 |
357269 |
62 |
0 |
0 |
| T6 |
5053890 |
80 |
0 |
0 |
| T7 |
5336776 |
102 |
0 |
0 |
| T8 |
14141115 |
62 |
0 |
0 |
| T9 |
1466080 |
62 |
0 |
0 |
| T10 |
6872251 |
215 |
0 |
0 |
| T11 |
5384333 |
80 |
0 |
0 |
| T12 |
38097 |
34 |
0 |
0 |
| T13 |
0 |
38 |
0 |
0 |
| T14 |
0 |
102 |
0 |
0 |
| T15 |
0 |
68 |
0 |
0 |
| T16 |
0 |
68 |
0 |
0 |
| T17 |
0 |
34 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T19 |
184870 |
0 |
0 |
0 |
| T20 |
38301 |
0 |
0 |
0 |
| T21 |
422160 |
0 |
0 |
0 |
| T22 |
13204560 |
0 |
0 |
0 |
| T23 |
6564243 |
0 |
0 |
0 |
| T24 |
8756140 |
20 |
0 |
0 |
| T36 |
0 |
32 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T40 |
6131 |
0 |
0 |
0 |
| T41 |
941 |
10 |
0 |
0 |
| T42 |
70 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 5 | 2 | 40.00 |
| Logical | 5 | 2 | 40.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 5 | 2 | 40.00 |
| Logical | 5 | 2 | 40.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Unreachable | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 6 | 75.00 |
| Logical | 8 | 6 | 75.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Not Covered | |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
82 |
0 |
0 |
| T6 |
1014 |
1 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
1 |
0 |
0 |
| T11 |
6317 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T25 |
0 |
1 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T43 |
0 |
1 |
0 |
0 |
| T44 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
388 |
0 |
0 |
| T6 |
296214 |
5 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
9 |
0 |
0 |
| T11 |
329809 |
8 |
0 |
0 |
| T13 |
0 |
5 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T25 |
0 |
10 |
0 |
0 |
| T36 |
0 |
5 |
0 |
0 |
| T38 |
0 |
9 |
0 |
0 |
| T39 |
0 |
5 |
0 |
0 |
| T43 |
0 |
9 |
0 |
0 |
| T44 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
32593 |
0 |
0 |
| T1 |
1148 |
41 |
0 |
0 |
| T2 |
86 |
0 |
0 |
0 |
| T3 |
1149 |
41 |
0 |
0 |
| T4 |
670 |
23 |
0 |
0 |
| T5 |
717 |
27 |
0 |
0 |
| T6 |
1014 |
6 |
0 |
0 |
| T7 |
1156 |
41 |
0 |
0 |
| T8 |
6346 |
31 |
0 |
0 |
| T9 |
0 |
27 |
0 |
0 |
| T10 |
0 |
48 |
0 |
0 |
| T11 |
0 |
8 |
0 |
0 |
| T19 |
747 |
0 |
0 |
0 |
| T20 |
97 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
32702 |
0 |
0 |
| T1 |
275894 |
41 |
0 |
0 |
| T2 |
21894 |
0 |
0 |
0 |
| T3 |
63265 |
41 |
0 |
0 |
| T4 |
26861 |
23 |
0 |
0 |
| T5 |
355835 |
27 |
0 |
0 |
| T6 |
296214 |
8 |
0 |
0 |
| T7 |
312704 |
41 |
0 |
0 |
| T8 |
825111 |
31 |
0 |
0 |
| T9 |
0 |
27 |
0 |
0 |
| T10 |
0 |
49 |
0 |
0 |
| T11 |
0 |
8 |
0 |
0 |
| T19 |
183376 |
0 |
0 |
0 |
| T20 |
38107 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
32648 |
0 |
0 |
| T1 |
275894 |
41 |
0 |
0 |
| T2 |
21894 |
0 |
0 |
0 |
| T3 |
63265 |
41 |
0 |
0 |
| T4 |
26861 |
23 |
0 |
0 |
| T5 |
355835 |
27 |
0 |
0 |
| T6 |
296214 |
7 |
0 |
0 |
| T7 |
312704 |
41 |
0 |
0 |
| T8 |
825111 |
31 |
0 |
0 |
| T9 |
0 |
27 |
0 |
0 |
| T10 |
0 |
48 |
0 |
0 |
| T11 |
0 |
8 |
0 |
0 |
| T19 |
183376 |
0 |
0 |
0 |
| T20 |
38107 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
32659 |
0 |
0 |
| T1 |
1148 |
41 |
0 |
0 |
| T2 |
86 |
0 |
0 |
0 |
| T3 |
1149 |
41 |
0 |
0 |
| T4 |
670 |
23 |
0 |
0 |
| T5 |
717 |
27 |
0 |
0 |
| T6 |
1014 |
7 |
0 |
0 |
| T7 |
1156 |
41 |
0 |
0 |
| T8 |
6346 |
31 |
0 |
0 |
| T9 |
0 |
27 |
0 |
0 |
| T10 |
0 |
48 |
0 |
0 |
| T11 |
0 |
8 |
0 |
0 |
| T19 |
747 |
0 |
0 |
0 |
| T20 |
97 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
15814 |
0 |
0 |
| T1 |
1148 |
1 |
0 |
0 |
| T2 |
86 |
0 |
0 |
0 |
| T3 |
1149 |
1 |
0 |
0 |
| T4 |
670 |
11 |
0 |
0 |
| T5 |
717 |
13 |
0 |
0 |
| T6 |
1014 |
5 |
0 |
0 |
| T7 |
1156 |
1 |
0 |
0 |
| T8 |
6346 |
15 |
0 |
0 |
| T9 |
0 |
13 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
6 |
0 |
0 |
| T19 |
747 |
0 |
0 |
0 |
| T20 |
97 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
15875 |
0 |
0 |
| T1 |
275894 |
1 |
0 |
0 |
| T2 |
21894 |
0 |
0 |
0 |
| T3 |
63265 |
1 |
0 |
0 |
| T4 |
26861 |
11 |
0 |
0 |
| T5 |
355835 |
13 |
0 |
0 |
| T6 |
296214 |
5 |
0 |
0 |
| T7 |
312704 |
1 |
0 |
0 |
| T8 |
825111 |
15 |
0 |
0 |
| T9 |
0 |
13 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
6 |
0 |
0 |
| T19 |
183376 |
0 |
0 |
0 |
| T20 |
38107 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
15862 |
0 |
0 |
| T1 |
275894 |
1 |
0 |
0 |
| T2 |
21894 |
0 |
0 |
0 |
| T3 |
63265 |
1 |
0 |
0 |
| T4 |
26861 |
11 |
0 |
0 |
| T5 |
355835 |
13 |
0 |
0 |
| T6 |
296214 |
5 |
0 |
0 |
| T7 |
312704 |
1 |
0 |
0 |
| T8 |
825111 |
15 |
0 |
0 |
| T9 |
0 |
13 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
6 |
0 |
0 |
| T19 |
183376 |
0 |
0 |
0 |
| T20 |
38107 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
15862 |
0 |
0 |
| T1 |
1148 |
1 |
0 |
0 |
| T2 |
86 |
0 |
0 |
0 |
| T3 |
1149 |
1 |
0 |
0 |
| T4 |
670 |
11 |
0 |
0 |
| T5 |
717 |
13 |
0 |
0 |
| T6 |
1014 |
5 |
0 |
0 |
| T7 |
1156 |
1 |
0 |
0 |
| T8 |
6346 |
15 |
0 |
0 |
| T9 |
0 |
13 |
0 |
0 |
| T10 |
0 |
11 |
0 |
0 |
| T11 |
0 |
6 |
0 |
0 |
| T19 |
747 |
0 |
0 |
0 |
| T20 |
97 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T2,T19,T20 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T2,T19,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
12812 |
0 |
0 |
| T2 |
86 |
1 |
0 |
0 |
| T3 |
1149 |
0 |
0 |
0 |
| T4 |
670 |
0 |
0 |
0 |
| T5 |
717 |
0 |
0 |
0 |
| T6 |
1014 |
4 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
747 |
1 |
0 |
0 |
| T20 |
97 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12917 |
0 |
0 |
| T2 |
21894 |
1 |
0 |
0 |
| T3 |
63265 |
0 |
0 |
0 |
| T4 |
26861 |
0 |
0 |
0 |
| T5 |
355835 |
0 |
0 |
0 |
| T6 |
296214 |
4 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
183376 |
1 |
0 |
0 |
| T20 |
38107 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T2,T19,T20 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T2,T19,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12875 |
0 |
0 |
| T2 |
21894 |
1 |
0 |
0 |
| T3 |
63265 |
0 |
0 |
0 |
| T4 |
26861 |
0 |
0 |
0 |
| T5 |
355835 |
0 |
0 |
0 |
| T6 |
296214 |
4 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
183376 |
1 |
0 |
0 |
| T20 |
38107 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
12875 |
0 |
0 |
| T2 |
86 |
1 |
0 |
0 |
| T3 |
1149 |
0 |
0 |
0 |
| T4 |
670 |
0 |
0 |
0 |
| T5 |
717 |
0 |
0 |
0 |
| T6 |
1014 |
4 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
747 |
1 |
0 |
0 |
| T20 |
97 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T2,T19,T20 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T2,T19,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
12792 |
0 |
0 |
| T2 |
86 |
1 |
0 |
0 |
| T3 |
1149 |
0 |
0 |
0 |
| T4 |
670 |
0 |
0 |
0 |
| T5 |
717 |
0 |
0 |
0 |
| T6 |
1014 |
4 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
747 |
1 |
0 |
0 |
| T20 |
97 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12899 |
0 |
0 |
| T2 |
21894 |
1 |
0 |
0 |
| T3 |
63265 |
0 |
0 |
0 |
| T4 |
26861 |
0 |
0 |
0 |
| T5 |
355835 |
0 |
0 |
0 |
| T6 |
296214 |
4 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
183376 |
1 |
0 |
0 |
| T20 |
38107 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T2,T19,T20 |
| 1 | 1 | Covered | T13,T14,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T19,T20 |
| 1 | 0 | Covered | T13,T14,T15 |
| 1 | 1 | Covered | T2,T19,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
12857 |
0 |
0 |
| T2 |
21894 |
1 |
0 |
0 |
| T3 |
63265 |
0 |
0 |
0 |
| T4 |
26861 |
0 |
0 |
0 |
| T5 |
355835 |
0 |
0 |
0 |
| T6 |
296214 |
4 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
183376 |
1 |
0 |
0 |
| T20 |
38107 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
12857 |
0 |
0 |
| T2 |
86 |
1 |
0 |
0 |
| T3 |
1149 |
0 |
0 |
0 |
| T4 |
670 |
0 |
0 |
0 |
| T5 |
717 |
0 |
0 |
0 |
| T6 |
1014 |
4 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
0 |
6 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T19 |
747 |
1 |
0 |
0 |
| T20 |
97 |
1 |
0 |
0 |
| T21 |
0 |
1 |
0 |
0 |
| T22 |
0 |
1 |
0 |
0 |
| T23 |
0 |
1 |
0 |
0 |
| T42 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T12,T13 |
| 1 | 0 | Covered | T10,T12,T13 |
| 1 | 1 | Covered | T10,T12,T14 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T12,T13 |
| 1 | 0 | Covered | T10,T12,T14 |
| 1 | 1 | Covered | T10,T12,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
18213 |
0 |
0 |
| T10 |
40411 |
2 |
0 |
0 |
| T11 |
6317 |
0 |
0 |
0 |
| T12 |
38097 |
2 |
0 |
0 |
| T13 |
19404 |
2 |
0 |
0 |
| T14 |
98248 |
6 |
0 |
0 |
| T15 |
0 |
4 |
0 |
0 |
| T16 |
0 |
4 |
0 |
0 |
| T17 |
0 |
2 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T38 |
0 |
13 |
0 |
0 |
| T40 |
6131 |
0 |
0 |
0 |
| T41 |
941 |
0 |
0 |
0 |
| T42 |
70 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
18268 |
0 |
0 |
| T10 |
386579 |
2 |
0 |
0 |
| T11 |
329809 |
0 |
0 |
0 |
| T12 |
171441 |
2 |
0 |
0 |
| T13 |
236299 |
2 |
0 |
0 |
| T14 |
210446 |
6 |
0 |
0 |
| T15 |
0 |
4 |
0 |
0 |
| T16 |
0 |
4 |
0 |
0 |
| T17 |
0 |
2 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T38 |
0 |
13 |
0 |
0 |
| T40 |
766469 |
0 |
0 |
0 |
| T41 |
117799 |
0 |
0 |
0 |
| T42 |
35137 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T12,T13 |
| 1 | 0 | Covered | T10,T12,T13 |
| 1 | 1 | Covered | T10,T12,T14 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T12,T13 |
| 1 | 0 | Covered | T10,T12,T14 |
| 1 | 1 | Covered | T10,T12,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
18260 |
0 |
0 |
| T10 |
386579 |
2 |
0 |
0 |
| T11 |
329809 |
0 |
0 |
0 |
| T12 |
171441 |
2 |
0 |
0 |
| T13 |
236299 |
2 |
0 |
0 |
| T14 |
210446 |
6 |
0 |
0 |
| T15 |
0 |
4 |
0 |
0 |
| T16 |
0 |
4 |
0 |
0 |
| T17 |
0 |
2 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T38 |
0 |
13 |
0 |
0 |
| T40 |
766469 |
0 |
0 |
0 |
| T41 |
117799 |
0 |
0 |
0 |
| T42 |
35137 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
18260 |
0 |
0 |
| T10 |
40411 |
2 |
0 |
0 |
| T11 |
6317 |
0 |
0 |
0 |
| T12 |
38097 |
2 |
0 |
0 |
| T13 |
19404 |
2 |
0 |
0 |
| T14 |
98248 |
6 |
0 |
0 |
| T15 |
0 |
4 |
0 |
0 |
| T16 |
0 |
4 |
0 |
0 |
| T17 |
0 |
2 |
0 |
0 |
| T18 |
0 |
4 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T37 |
0 |
2 |
0 |
0 |
| T38 |
0 |
13 |
0 |
0 |
| T40 |
6131 |
0 |
0 |
0 |
| T41 |
941 |
0 |
0 |
0 |
| T42 |
70 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1942 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
4 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1998 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
4 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1989 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
4 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1989 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
4 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1817 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1876 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1866 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1866 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1772 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1829 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1820 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1820 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1783 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1838 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1828 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1828 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1801 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1857 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1848 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1848 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1778 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1831 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1823 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1823 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1823 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1877 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1868 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1868 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1792 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1848 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1838 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1838 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1896 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
4 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1950 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
4 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1941 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
4 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1941 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
4 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1810 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1862 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1855 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1855 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1802 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1857 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1848 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1848 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1762 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1821 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1810 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1810 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1796 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1854 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1846 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1846 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1790 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1845 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1837 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1837 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1807 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1864 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1854 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1854 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1806 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1863 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T15,T16 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T15,T16 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1853 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
3 |
0 |
0 |
| T11 |
329809 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1853 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
3 |
0 |
0 |
| T11 |
6317 |
2 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T15 |
0 |
2 |
0 |
0 |
| T16 |
0 |
2 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T36 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T45,T130 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T45,T130 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1327 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
2 |
0 |
0 |
| T11 |
6317 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T34 |
0 |
1 |
0 |
0 |
| T45 |
0 |
3 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1384 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
2 |
0 |
0 |
| T11 |
329809 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T34 |
0 |
1 |
0 |
0 |
| T45 |
0 |
3 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T6,T10,T11 |
| 1 | 1 | Covered | T14,T45,T130 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T10,T11 |
| 1 | 0 | Covered | T14,T45,T130 |
| 1 | 1 | Covered | T6,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
1374 |
0 |
0 |
| T6 |
296214 |
2 |
0 |
0 |
| T7 |
312704 |
0 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
90904 |
0 |
0 |
0 |
| T10 |
386579 |
2 |
0 |
0 |
| T11 |
329809 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
26318 |
0 |
0 |
0 |
| T22 |
823639 |
0 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T34 |
0 |
1 |
0 |
0 |
| T45 |
0 |
3 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
1374 |
0 |
0 |
| T6 |
1014 |
2 |
0 |
0 |
| T7 |
1156 |
0 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
726 |
0 |
0 |
0 |
| T10 |
40411 |
2 |
0 |
0 |
| T11 |
6317 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
0 |
3 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T21 |
67 |
0 |
0 |
0 |
| T22 |
1646 |
0 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T34 |
0 |
1 |
0 |
0 |
| T45 |
0 |
3 |
0 |
0 |
| T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T11,T12 |
| 1 | 0 | Covered | T10,T11,T12 |
| 1 | 1 | Covered | T12,T14,T15 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T10,T11,T12 |
| 1 | 0 | Covered | T12,T14,T15 |
| 1 | 1 | Covered | T10,T11,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283660 |
64313 |
0 |
0 |
| T10 |
40411 |
1 |
0 |
0 |
| T11 |
6317 |
1 |
0 |
0 |
| T12 |
38097 |
77 |
0 |
0 |
| T13 |
19404 |
1 |
0 |
0 |
| T14 |
98248 |
138 |
0 |
0 |
| T15 |
0 |
143 |
0 |
0 |
| T16 |
0 |
142 |
0 |
0 |
| T17 |
0 |
78 |
0 |
0 |
| T18 |
0 |
144 |
0 |
0 |
| T23 |
851 |
0 |
0 |
0 |
| T24 |
1148 |
0 |
0 |
0 |
| T37 |
0 |
93 |
0 |
0 |
| T40 |
6131 |
0 |
0 |
0 |
| T41 |
941 |
0 |
0 |
0 |
| T42 |
70 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
64370 |
0 |
0 |
| T10 |
386579 |
1 |
0 |
0 |
| T11 |
329809 |
1 |
0 |
0 |
| T12 |
171441 |
77 |
0 |
0 |
| T13 |
236299 |
1 |
0 |
0 |
| T14 |
210446 |
138 |
0 |
0 |
| T15 |
0 |
143 |
0 |
0 |
| T16 |
0 |
142 |
0 |
0 |
| T17 |
0 |
78 |
0 |
0 |
| T18 |
0 |
144 |
0 |
0 |
| T23 |
409361 |
0 |
0 |
0 |
| T24 |
546039 |
0 |
0 |
0 |
| T37 |
0 |
93 |
0 |
0 |
| T40 |
766469 |
0 |
0 |
0 |
| T41 |
117799 |
0 |
0 |
0 |
| T42 |
35137 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T3,T4 |
| 1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_oneshot_done_sync
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
5096 |
0 |
0 |
| T1 |
275894 |
20 |
0 |
0 |
| T2 |
21894 |
0 |
0 |
0 |
| T3 |
63265 |
20 |
0 |
0 |
| T4 |
26861 |
8 |
0 |
0 |
| T5 |
355835 |
8 |
0 |
0 |
| T6 |
296214 |
1 |
0 |
0 |
| T7 |
312704 |
20 |
0 |
0 |
| T8 |
825111 |
0 |
0 |
0 |
| T9 |
0 |
8 |
0 |
0 |
| T10 |
0 |
16 |
0 |
0 |
| T19 |
183376 |
0 |
0 |
0 |
| T20 |
38107 |
0 |
0 |
0 |
| T24 |
0 |
20 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32201721 |
5099 |
0 |
0 |
| T1 |
1148 |
20 |
0 |
0 |
| T2 |
86 |
0 |
0 |
0 |
| T3 |
1149 |
20 |
0 |
0 |
| T4 |
670 |
8 |
0 |
0 |
| T5 |
717 |
8 |
0 |
0 |
| T6 |
1014 |
1 |
0 |
0 |
| T7 |
1156 |
20 |
0 |
0 |
| T8 |
6346 |
0 |
0 |
0 |
| T9 |
0 |
8 |
0 |
0 |
| T10 |
0 |
16 |
0 |
0 |
| T19 |
747 |
0 |
0 |
0 |
| T20 |
97 |
0 |
0 |
0 |
| T24 |
0 |
20 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |