Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2196	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2074	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1788	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1920	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1944	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1909	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2081	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2060	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1909	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2019	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2032	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2166	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2115	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2023	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2177	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2007	0	0
adc_en_ctl_rd_A	2147483647	1685	0	0
adc_fsm_rst_rd_A	2147483647	1449	0	0
adc_intr_ctl_rd_A	2147483647	2423	0	0
adc_lp_sample_ctl_rd_A	2147483647	1458	0	0
adc_pd_ctl_rd_A	2147483647	1682	0	0
adc_sample_ctl_rd_A	2147483647	1660	0	0
adc_wakeup_ctl_rd_A	2147483647	1635	0	0
intr_enable_rd_A	2147483647	2492	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2196	0	0
T6	296214	17	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	18	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	23	0	0
T26	0	19	0	0
T27	0	14	0	0
T28	0	30	0	0
T29	0	31	0	0
T30	0	12	0	0
T31	0	47	0	0
T32	0	35	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2074	0	0
T6	296214	12	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	21	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	32	0	0
T26	0	18	0	0
T27	0	13	0	0
T28	0	34	0	0
T29	0	11	0	0
T30	0	18	0	0
T31	0	43	0	0
T32	0	46	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1788	0	0
T6	296214	14	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	27	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	18	0	0
T26	0	12	0	0
T27	0	7	0	0
T28	0	39	0	0
T29	0	4	0	0
T30	0	21	0	0
T31	0	34	0	0
T32	0	39	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1920	0	0
T6	296214	19	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	8	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	32	0	0
T26	0	22	0	0
T27	0	21	0	0
T28	0	28	0	0
T29	0	6	0	0
T30	0	7	0	0
T31	0	38	0	0
T32	0	27	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1944	0	0
T6	296214	15	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	20	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	22	0	0
T26	0	23	0	0
T27	0	10	0	0
T28	0	42	0	0
T29	0	14	0	0
T30	0	9	0	0
T31	0	38	0	0
T32	0	31	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1909	0	0
T6	296214	29	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	23	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	28	0	0
T26	0	3	0	0
T27	0	4	0	0
T28	0	27	0	0
T29	0	11	0	0
T30	0	8	0	0
T31	0	53	0	0
T32	0	19	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2081	0	0
T6	296214	30	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	22	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	11	0	0
T26	0	7	0	0
T27	0	23	0	0
T28	0	35	0	0
T29	0	14	0	0
T30	0	29	0	0
T31	0	38	0	0
T32	0	43	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2060	0	0
T6	296214	16	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	22	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	25	0	0
T26	0	31	0	0
T27	0	20	0	0
T28	0	48	0	0
T29	0	10	0	0
T30	0	14	0	0
T31	0	20	0	0
T32	0	41	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1909	0	0
T6	296214	12	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	19	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	19	0	0
T26	0	26	0	0
T27	0	6	0	0
T28	0	28	0	0
T29	0	7	0	0
T30	0	27	0	0
T31	0	42	0	0
T32	0	24	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2019	0	0
T6	296214	21	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	25	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	30	0	0
T26	0	7	0	0
T27	0	18	0	0
T28	0	39	0	0
T29	0	13	0	0
T30	0	7	0	0
T31	0	42	0	0
T32	0	35	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2032	0	0
T6	296214	10	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	26	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	25	0	0
T26	0	16	0	0
T27	0	27	0	0
T28	0	35	0	0
T29	0	7	0	0
T30	0	27	0	0
T31	0	26	0	0
T32	0	39	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2166	0	0
T6	296214	14	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	21	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	35	0	0
T26	0	18	0	0
T27	0	14	0	0
T28	0	33	0	0
T29	0	12	0	0
T30	0	19	0	0
T31	0	44	0	0
T32	0	30	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T6	296214	23	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	16	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	17	0	0
T26	0	22	0	0
T27	0	12	0	0
T28	0	44	0	0
T29	0	4	0	0
T30	0	21	0	0
T31	0	38	0	0
T32	0	23	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2023	0	0
T6	296214	19	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	17	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	15	0	0
T26	0	22	0	0
T27	0	15	0	0
T28	0	22	0	0
T29	0	8	0	0
T30	0	18	0	0
T31	0	32	0	0
T32	0	41	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2177	0	0
T6	296214	20	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	15	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	40	0	0
T26	0	23	0	0
T27	0	13	0	0
T28	0	30	0	0
T29	0	25	0	0
T30	0	14	0	0
T31	0	45	0	0
T32	0	41	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2007	0	0
T6	296214	9	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	21	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	13	0	0
T26	0	19	0	0
T27	0	13	0	0
T28	0	27	0	0
T29	0	9	0	0
T30	0	12	0	0
T31	0	21	0	0
T32	0	32	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1685	0	0
T6	296214	19	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	21	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	13	0	0
T26	0	17	0	0
T27	0	10	0	0
T28	0	42	0	0
T29	0	6	0	0
T30	0	30	0	0
T31	0	41	0	0
T32	0	29	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1449	0	0
T6	296214	2	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	11	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	8	0	0
T26	0	27	0	0
T27	0	14	0	0
T28	0	44	0	0
T30	0	8	0	0
T31	0	29	0	0
T32	0	29	0	0
T33	0	13	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2423	0	0
T6	296214	25	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	27	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	20	0	0
T26	0	17	0	0
T27	0	27	0	0
T28	0	47	0	0
T29	0	4	0	0
T30	0	12	0	0
T31	0	33	0	0
T32	0	40	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1458	0	0
T6	296214	17	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	22	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	26	0	0
T26	0	14	0	0
T27	0	18	0	0
T28	0	35	0	0
T29	0	14	0	0
T30	0	22	0	0
T31	0	54	0	0
T32	0	47	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1682	0	0
T6	296214	15	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	10	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	17	0	0
T26	0	16	0	0
T27	0	16	0	0
T28	0	39	0	0
T29	0	4	0	0
T30	0	14	0	0
T31	0	48	0	0
T32	0	40	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1660	0	0
T6	296214	18	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	13	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	22	0	0
T26	0	29	0	0
T27	0	10	0	0
T28	0	39	0	0
T29	0	15	0	0
T30	0	22	0	0
T31	0	32	0	0
T32	0	33	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T6	296214	18	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	11	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	15	0	0
T26	0	26	0	0
T27	0	14	0	0
T28	0	38	0	0
T29	0	12	0	0
T30	0	20	0	0
T31	0	39	0	0
T32	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2492	0	0
T6	296214	30	0	0
T7	312704	0	0	0
T8	825111	0	0	0
T9	90904	0	0	0
T10	386579	0	0	0
T11	329809	0	0	0
T13	0	34	0	0
T21	26318	0	0	0
T22	823639	0	0	0
T23	409361	0	0	0
T24	546039	0	0	0
T25	0	29	0	0
T26	0	16	0	0
T27	0	17	0	0
T28	0	40	0	0
T29	0	36	0	0
T30	0	17	0	0
T34	0	12	0	0
T35	0	28	0	0