Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	5400	1			T2	20		T3	20		T5	6
testmodes[AdcCtrlTestmodeNormal]	4582	1			T4	1		T5	4		T7	6
testmodes[AdcCtrlTestmodeLowpower]	4937	1			T6	10		T8	10		T10	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	2712	1			T2	19		T3	19		T5	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1378	1			T5	2		T7	4		T10	7
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1191	1			T42	1		T52	9		T50	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1416	1			T5	2		T7	3		T10	7
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1669	1			T5	2		T7	2		T10	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1165	1			T10	1		T15	1		T42	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1151	1			T42	2		T52	6		T50	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1199	1			T15	1		T42	1		T120	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2342	1			T6	9		T8	9		T40	13