Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6878	1			T2	20		T3	20		T4	11
testmodes[AdcCtrlTestmodeNormal]	5307	1			T4	8		T5	6		T8	9
testmodes[AdcCtrlTestmodeLowpower]	5546	1			T6	13		T11	17		T12	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3806	1			T2	19		T3	19		T4	8
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1670	1			T4	3		T5	3		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1290	1			T18	2		T41	2		T49	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1685	1			T4	2		T5	2		T8	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1977	1			T4	5		T5	3		T8	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1301	1			T15	1		T18	1		T41	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1276	1			T18	1		T41	3		T49	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1322	1			T12	1		T18	2		T49	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2706	1			T6	12		T11	16		T12	1