Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.64


Total tests in report: 918
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
55.96 55.96 88.15 88.15 49.86 49.86 83.89 83.89 27.03 27.03 73.18 73.18 64.27 64.27 5.37 5.37 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.4206121879
78.23 22.26 98.12 9.97 91.72 41.87 91.94 8.06 56.76 29.73 97.34 24.17 90.32 26.04 21.39 16.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.967905407
82.71 4.48 98.40 0.28 93.17 1.44 92.89 0.95 72.97 16.22 97.71 0.37 94.99 4.67 28.82 7.44 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1770326234
85.59 2.89 98.77 0.37 93.95 0.78 96.92 4.03 86.49 13.51 98.45 0.74 95.66 0.67 28.92 0.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3478389074
87.97 2.38 98.89 0.12 94.36 0.41 96.92 0.00 91.89 5.41 98.58 0.12 95.66 0.00 39.51 10.58 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.261900392
89.45 1.47 98.89 0.00 94.36 0.00 97.16 0.24 94.59 2.70 98.58 0.00 95.83 0.17 46.72 7.21 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.640173734
90.49 1.04 98.89 0.00 94.36 0.00 97.16 0.00 97.30 2.70 98.58 0.00 95.83 0.00 51.31 4.59 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_both.1756561491
91.28 0.80 98.89 0.00 94.36 0.00 97.16 0.00 97.30 0.00 98.58 0.00 95.83 0.00 56.88 5.57 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3013445242
91.90 0.61 98.89 0.00 94.36 0.00 97.16 0.00 100.00 2.70 98.58 0.00 95.83 0.00 58.47 1.60 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all.1972229213
92.43 0.53 98.89 0.00 94.36 0.00 97.16 0.00 100.00 0.00 98.58 0.00 95.83 0.00 62.17 3.69 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.145727322
92.88 0.46 98.89 0.00 95.72 1.36 97.63 0.47 100.00 0.00 98.64 0.06 96.49 0.67 62.82 0.65 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_errors.368408014
93.32 0.43 98.89 0.00 95.72 0.00 97.63 0.00 100.00 0.00 98.64 0.00 96.49 0.00 65.83 3.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.3672547812
93.69 0.38 98.92 0.03 95.84 0.12 99.76 2.13 100.00 0.00 98.70 0.06 96.66 0.17 65.96 0.12 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.2822548319
94.03 0.34 98.92 0.00 95.84 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.66 0.00 68.33 2.37 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1727717077
94.35 0.32 98.92 0.00 95.84 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.33 70.20 1.87 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1695062879
94.63 0.29 98.92 0.00 95.92 0.08 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 72.12 1.92 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1665221808
94.89 0.26 98.92 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 73.95 1.82 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2603931543
95.12 0.22 98.92 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 75.52 1.57 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_both.196769148
95.33 0.22 98.92 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 77.04 1.52 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2082107938
95.52 0.19 98.92 0.00 95.92 0.00 99.76 0.00 100.00 0.00 98.70 0.00 96.99 0.00 78.34 1.30 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1927381499
95.70 0.18 98.98 0.06 96.17 0.25 99.76 0.00 100.00 0.00 98.83 0.12 97.83 0.83 78.34 0.00 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3932108857
95.86 0.16 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 79.44 1.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3071105230
95.98 0.12 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 80.31 0.87 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3190497788
96.10 0.12 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 81.13 0.82 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2734349725
96.20 0.10 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 81.83 0.70 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2015397987
96.30 0.10 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 82.51 0.67 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2148766634
96.39 0.09 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 83.13 0.62 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/32.adc_ctrl_filters_wakeup.2867659249
96.46 0.08 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 83.68 0.55 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1142580728
96.54 0.07 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 84.20 0.52 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/29.adc_ctrl_stress_all.1192100474
96.61 0.07 98.98 0.00 96.17 0.00 99.76 0.00 100.00 0.00 98.83 0.00 97.83 0.00 84.68 0.47 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/41.adc_ctrl_clock_gating.3831093125
96.67 0.06 99.07 0.09 96.29 0.12 100.00 0.24 100.00 0.00 98.83 0.00 97.83 0.00 84.68 0.00 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3186017340
96.73 0.06 99.07 0.00 96.29 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 85.10 0.42 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup.2059649818
96.79 0.06 99.07 0.00 96.54 0.25 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 85.28 0.17 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1836424974
96.85 0.06 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 85.68 0.40 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.410555339
96.90 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 86.05 0.37 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2798005814
96.96 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 86.42 0.37 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3818419144
97.01 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 86.77 0.35 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt.1810014803
97.06 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 87.12 0.35 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1152799640
97.11 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 97.83 0.00 87.47 0.35 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_wakeup.772861343
97.15 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.33 87.47 0.00 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4275962744
97.20 0.05 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 87.80 0.32 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_both.887455096
97.24 0.04 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 88.05 0.25 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.263350239
97.27 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 88.27 0.22 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1838674090
97.30 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 88.50 0.22 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/23.adc_ctrl_clock_gating.3865377586
97.33 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 88.72 0.22 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/40.adc_ctrl_filters_both.4265908206
97.36 0.03 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 88.92 0.20 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_clock_gating.1926895884
97.39 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 89.09 0.17 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt.2212314254
97.41 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.16 0.00 89.27 0.17 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_filters_both.2693208085
97.43 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.17 89.27 0.00 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3856593751
97.46 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.42 0.15 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.655292033
97.48 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.57 0.15 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/26.adc_ctrl_filters_wakeup.293284387
97.50 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.72 0.15 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_clock_gating.3314882274
97.52 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.84 0.12 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4028331960
97.53 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 89.97 0.12 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3941541152
97.55 0.02 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.09 0.12 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup.1195312232
97.57 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.19 0.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1219600265
97.58 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.29 0.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/43.adc_ctrl_filters_interrupt.2784885436
97.59 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.39 0.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/49.adc_ctrl_clock_gating.935999169
97.61 0.01 99.07 0.00 96.54 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.49 0.10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3578472922
97.62 0.01 99.07 0.00 96.62 0.08 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.49 0.00 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_errors.375016844
97.63 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.57 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.523515669
97.64 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.64 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1240590086
97.65 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.72 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_clock_gating.1054072182
97.66 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.79 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1296488023
97.67 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.87 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/31.adc_ctrl_filters_interrupt.3634941669
97.69 0.01 99.07 0.00 96.62 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.94 0.07 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.231363993
97.69 0.01 99.07 0.00 96.67 0.04 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 90.97 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3181106977
97.70 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.02 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1202373769
97.71 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.07 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_both.2870378823
97.72 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.12 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all.2317651522
97.72 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.17 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_both.3633420832
97.73 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.22 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/35.adc_ctrl_filters_interrupt.673710532
97.74 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.27 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.66694086
97.74 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.32 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/42.adc_ctrl_filters_both.138917955
97.75 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.37 0.05 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1907649773
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.39 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1969746654
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.42 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3682644705
97.76 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.44 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3007132781
97.77 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.46 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.572564731
97.77 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.49 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_both.1797370946
97.77 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.51 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/24.adc_ctrl_stress_all.846664164
97.78 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.54 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.567491568
97.78 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.56 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/37.adc_ctrl_fsm_reset.3803408614
97.78 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.59 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/38.adc_ctrl_stress_all.420841345
97.79 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.61 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.4270735091
97.79 0.01 99.07 0.00 96.67 0.00 100.00 0.00 100.00 0.00 98.83 0.00 98.33 0.00 91.64 0.02 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/44.adc_ctrl_filters_wakeup.3394218250

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3408227608
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1034985249
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_intr_test.1503560207
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3083870203
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2117146713
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2884035965
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2697747577
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.932984534
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1158813466
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_intr_test.1454296406
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3843151505
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.574925675
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3508489314
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3015989235
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_intr_test.3601896866
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3087574642
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3534582882
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2574007133
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3275732306
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_csr_rw.872626820
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_intr_test.3801586755
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.474326531
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4027905157
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.4182165928
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2044604949
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_csr_rw.859910785
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_intr_test.2865217110
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1284331279
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2108688915
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3863528822
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3709328761
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1424992821
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_intr_test.2995173462
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2278559160
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1503258050
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1081047225
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1533409603
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1186966455
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_intr_test.3917523398
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2245630822
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3289090320
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2810192473
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1022948100
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_csr_rw.424279674
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_intr_test.3074599558
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3606566646
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2474271748
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2027624238
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2737345264
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_intr_test.3168119121
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3554900972
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2667231971
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3403418451
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.931984338
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3627518440
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_intr_test.669231316
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1540652474
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3035110007
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1095551680
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2960849933
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3605611343
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_intr_test.18675848
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4039079707
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1001527516
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3530463052
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2706714730
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4150041648
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_intr_test.2212860686
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.433079720
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1352717315
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.685271432
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.85292226
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4180606644
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1407663959
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1618653670
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1295591031
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_intr_test.3662498572
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1558416835
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2262287580
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.994322345
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/20.adc_ctrl_intr_test.1413694725
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/21.adc_ctrl_intr_test.2486206493
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/22.adc_ctrl_intr_test.2742944089
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/23.adc_ctrl_intr_test.2922827817
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/24.adc_ctrl_intr_test.2586106170
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/25.adc_ctrl_intr_test.572947664
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/26.adc_ctrl_intr_test.36906834
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/27.adc_ctrl_intr_test.2981276526
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/28.adc_ctrl_intr_test.2664084664
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/29.adc_ctrl_intr_test.580027783
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3969811653
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.320626456
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2827551439
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1339705391
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_csr_rw.967071125
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_intr_test.3433818091
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4094614724
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_errors.852186120
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.931408452
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/30.adc_ctrl_intr_test.3409328122
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/31.adc_ctrl_intr_test.1256609466
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/32.adc_ctrl_intr_test.452698582
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/33.adc_ctrl_intr_test.4214032602
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/34.adc_ctrl_intr_test.1942472968
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/35.adc_ctrl_intr_test.2918053348
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/36.adc_ctrl_intr_test.299180612
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/37.adc_ctrl_intr_test.1129304650
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/38.adc_ctrl_intr_test.3515395580
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/39.adc_ctrl_intr_test.3663143084
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1898291154
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2974247515
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.21784392
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.175133623
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3219024020
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_intr_test.1903510943
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3077991182
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1250080670
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/40.adc_ctrl_intr_test.2552315345
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/41.adc_ctrl_intr_test.3162069404
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/42.adc_ctrl_intr_test.2409097174
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/43.adc_ctrl_intr_test.1087909474
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/44.adc_ctrl_intr_test.3878851117
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/45.adc_ctrl_intr_test.1122887559
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/46.adc_ctrl_intr_test.39941537
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/47.adc_ctrl_intr_test.1963241908
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/48.adc_ctrl_intr_test.2547885766
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/49.adc_ctrl_intr_test.20877436
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.328480380
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3253146555
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_intr_test.4179530693
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4040615903
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1542288620
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4028151757
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3464458421
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3307075829
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_intr_test.1385656592
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3828871008
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3608584109
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2755400431
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2697641443
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2818601801
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_intr_test.1975378251
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1776008414
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1017942177
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/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup.3063435877
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3414713202
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.34127373
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3541258494
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3499447640
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2860523190
/workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1389895212



Total test records in report: 918
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_alert_test.3186017340 Feb 08 10:19:55 AM UTC 25 Feb 08 10:20:00 AM UTC 25 523070790 ps
T2 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_smoke.1195026866 Feb 08 10:19:55 AM UTC 25 Feb 08 10:20:02 AM UTC 25 5654932379 ps
T3 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_smoke.1344833594 Feb 08 10:19:50 AM UTC 25 Feb 08 10:20:02 AM UTC 25 5499231133 ps
T4 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_poweron_counter.1439960522 Feb 08 10:19:51 AM UTC 25 Feb 08 10:20:05 AM UTC 25 5245968320 ps
T5 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_poweron_counter.2499244314 Feb 08 10:20:01 AM UTC 25 Feb 08 10:20:08 AM UTC 25 3216427672 ps
T6 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_lowpower_counter.4206121879 Feb 08 10:20:01 AM UTC 25 Feb 08 10:20:19 AM UTC 25 28966160650 ps
T21 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_alert_test.1419830167 Feb 08 10:20:16 AM UTC 25 Feb 08 10:20:19 AM UTC 25 463140728 ps
T22 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_sec_cm.2822548319 Feb 08 10:19:53 AM UTC 25 Feb 08 10:20:22 AM UTC 25 8202111953 ps
T7 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_smoke.3478389074 Feb 08 10:20:16 AM UTC 25 Feb 08 10:20:25 AM UTC 25 6048983127 ps
T23 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_sec_cm.2078570845 Feb 08 10:20:08 AM UTC 25 Feb 08 10:20:30 AM UTC 25 8032851316 ps
T8 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_poweron_counter.1273213528 Feb 08 10:20:27 AM UTC 25 Feb 08 10:20:35 AM UTC 25 4994011177 ps
T54 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_alert_test.2569621140 Feb 08 10:20:37 AM UTC 25 Feb 08 10:20:41 AM UTC 25 430506645 ps
T55 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_sec_cm.241256148 Feb 08 10:20:37 AM UTC 25 Feb 08 10:20:43 AM UTC 25 4099429795 ps
T9 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt.3682644705 Feb 08 10:19:50 AM UTC 25 Feb 08 10:20:50 AM UTC 25 170004431043 ps
T10 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_smoke.3910569411 Feb 08 10:20:42 AM UTC 25 Feb 08 10:20:51 AM UTC 25 5732630555 ps
T11 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_lowpower_counter.1243170310 Feb 08 10:19:52 AM UTC 25 Feb 08 10:20:55 AM UTC 25 39341807276 ps
T24 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_poweron_counter.1244114287 Feb 08 10:21:49 AM UTC 25 Feb 08 10:22:02 AM UTC 25 4100651822 ps
T12 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_clock_gating.967905407 Feb 08 10:19:59 AM UTC 25 Feb 08 10:22:02 AM UTC 25 506520519689 ps
T13 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled_fixed.2306769423 Feb 08 10:20:19 AM UTC 25 Feb 08 10:22:17 AM UTC 25 159298059904 ps
T25 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_lowpower_counter.2555297938 Feb 08 10:20:29 AM UTC 25 Feb 08 10:22:24 AM UTC 25 32362494281 ps
T26 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_alert_test.2977643383 Feb 08 10:22:24 AM UTC 25 Feb 08 10:22:29 AM UTC 25 461718099 ps
T27 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_sec_cm.2707080225 Feb 08 10:22:18 AM UTC 25 Feb 08 10:22:32 AM UTC 25 8188427002 ps
T28 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_smoke.2755558951 Feb 08 10:22:30 AM UTC 25 Feb 08 10:22:36 AM UTC 25 5950503066 ps
T58 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_lowpower_counter.355790945 Feb 08 10:21:54 AM UTC 25 Feb 08 10:22:45 AM UTC 25 42208607790 ps
T14 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt.3463566755 Feb 08 10:20:20 AM UTC 25 Feb 08 10:22:53 AM UTC 25 168632617787 ps
T15 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_clock_gating.1807052035 Feb 08 10:21:00 AM UTC 25 Feb 08 10:22:55 AM UTC 25 344184145847 ps
T16 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1665221808 Feb 08 10:20:23 AM UTC 25 Feb 08 10:23:29 AM UTC 25 204321792292 ps
T17 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2798005814 Feb 08 10:19:51 AM UTC 25 Feb 08 10:23:32 AM UTC 25 332764438321 ps
T130 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_poweron_counter.1034520072 Feb 08 10:23:26 AM UTC 25 Feb 08 10:23:35 AM UTC 25 4677209431 ps
T18 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1770326234 Feb 08 10:20:30 AM UTC 25 Feb 08 10:23:41 AM UTC 25 403110430197 ps
T19 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup.3457460661 Feb 08 10:22:55 AM UTC 25 Feb 08 10:23:43 AM UTC 25 178271478036 ps
T20 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup.523515669 Feb 08 10:19:51 AM UTC 25 Feb 08 10:23:44 AM UTC 25 178690123611 ps
T38 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_alert_test.1313180734 Feb 08 10:23:45 AM UTC 25 Feb 08 10:23:48 AM UTC 25 511787577 ps
T39 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_lowpower_counter.2209356282 Feb 08 10:23:26 AM UTC 25 Feb 08 10:23:58 AM UTC 25 44960778108 ps
T40 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_smoke.1266025140 Feb 08 10:23:45 AM UTC 25 Feb 08 10:24:00 AM UTC 25 5778670487 ps
T41 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2660266716 Feb 08 10:19:52 AM UTC 25 Feb 08 10:24:02 AM UTC 25 407557178502 ps
T42 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_sec_cm.3389438973 Feb 08 10:23:42 AM UTC 25 Feb 08 10:24:03 AM UTC 25 4452503583 ps
T43 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled_fixed.86086096 Feb 08 10:19:55 AM UTC 25 Feb 08 10:24:32 AM UTC 25 157980137050 ps
T44 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_poweron_counter.2713578097 Feb 08 10:24:35 AM UTC 25 Feb 08 10:24:39 AM UTC 25 4710031192 ps
T140 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled.805693988 Feb 08 10:19:50 AM UTC 25 Feb 08 10:24:53 AM UTC 25 316220586994 ps
T56 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_wakeup.344482995 Feb 08 10:20:23 AM UTC 25 Feb 08 10:25:03 AM UTC 25 348695764689 ps
T141 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled.4223557466 Feb 08 10:22:33 AM UTC 25 Feb 08 10:25:13 AM UTC 25 165141598899 ps
T57 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_clock_gating.2027155910 Feb 08 10:20:26 AM UTC 25 Feb 08 10:25:17 AM UTC 25 170523378983 ps
T148 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_alert_test.2265785377 Feb 08 10:25:15 AM UTC 25 Feb 08 10:25:17 AM UTC 25 352787995 ps
T132 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt.1283545341 Feb 08 10:19:55 AM UTC 25 Feb 08 10:25:19 AM UTC 25 330714208248 ps
T149 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_smoke.2128484967 Feb 08 10:25:18 AM UTC 25 Feb 08 10:25:26 AM UTC 25 5764494887 ps
T150 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_lowpower_counter.1487518164 Feb 08 10:24:40 AM UTC 25 Feb 08 10:25:37 AM UTC 25 44329856188 ps
T151 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1004574129 Feb 08 10:20:20 AM UTC 25 Feb 08 10:25:56 AM UTC 25 165499606598 ps
T49 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3071105230 Feb 08 10:20:02 AM UTC 25 Feb 08 10:26:10 AM UTC 25 323675276866 ps
T152 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled.345940262 Feb 08 10:20:44 AM UTC 25 Feb 08 10:26:18 AM UTC 25 494675467869 ps
T153 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_clock_gating.3611297256 Feb 08 10:24:26 AM UTC 25 Feb 08 10:26:19 AM UTC 25 163970250798 ps
T154 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_clock_gating.752358512 Feb 08 10:19:51 AM UTC 25 Feb 08 10:26:27 AM UTC 25 162103368855 ps
T201 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_poweron_counter.4021861558 Feb 08 10:26:20 AM UTC 25 Feb 08 10:26:27 AM UTC 25 3602821914 ps
T29 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.640173734 Feb 08 10:22:03 AM UTC 25 Feb 08 10:26:34 AM UTC 25 387731069884 ps
T270 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2376781803 Feb 08 10:24:03 AM UTC 25 Feb 08 10:26:49 AM UTC 25 493706873786 ps
T364 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_alert_test.123500008 Feb 08 10:26:50 AM UTC 25 Feb 08 10:26:54 AM UTC 25 357786654 ps
T50 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.410555339 Feb 08 10:24:55 AM UTC 25 Feb 08 10:27:04 AM UTC 25 114676395509 ps
T30 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2734349725 Feb 08 10:23:32 AM UTC 25 Feb 08 10:27:09 AM UTC 25 157019280458 ps
T365 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled_fixed.190641651 Feb 08 10:25:20 AM UTC 25 Feb 08 10:27:13 AM UTC 25 165684047962 ps
T133 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_polled.2027219872 Feb 08 10:19:55 AM UTC 25 Feb 08 10:27:20 AM UTC 25 164868833622 ps
T366 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_smoke.95330037 Feb 08 10:26:55 AM UTC 25 Feb 08 10:27:22 AM UTC 25 5795994044 ps
T367 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_polled_fixed.1917615226 Feb 08 10:22:37 AM UTC 25 Feb 08 10:27:27 AM UTC 25 167279722672 ps
T230 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_polled.3333421942 Feb 08 10:25:19 AM UTC 25 Feb 08 10:27:37 AM UTC 25 165278972479 ps
T159 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup.3369837197 Feb 08 10:19:56 AM UTC 25 Feb 08 10:27:37 AM UTC 25 181734925333 ps
T368 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_polled_fixed.3931710742 Feb 08 10:20:44 AM UTC 25 Feb 08 10:27:39 AM UTC 25 161513676433 ps
T160 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_both.2089687507 Feb 08 10:26:19 AM UTC 25 Feb 08 10:27:41 AM UTC 25 163838101776 ps
T369 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_poweron_counter.986251392 Feb 08 10:27:38 AM UTC 25 Feb 08 10:27:46 AM UTC 25 5231697207 ps
T222 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_clock_gating.526359404 Feb 08 10:27:27 AM UTC 25 Feb 08 10:27:47 AM UTC 25 162263327267 ps
T370 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1875545348 Feb 08 10:25:38 AM UTC 25 Feb 08 10:27:53 AM UTC 25 334523314351 ps
T371 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_alert_test.680335589 Feb 08 10:27:54 AM UTC 25 Feb 08 10:27:57 AM UTC 25 353085817 ps
T372 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_smoke.1444392077 Feb 08 10:27:58 AM UTC 25 Feb 08 10:28:07 AM UTC 25 5901157282 ps
T62 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_stress_all.864796760 Feb 08 10:19:52 AM UTC 25 Feb 08 10:28:15 AM UTC 25 150421833770 ps
T173 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup.2157107798 Feb 08 10:27:22 AM UTC 25 Feb 08 10:28:28 AM UTC 25 184247171717 ps
T373 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2480379871 Feb 08 10:19:55 AM UTC 25 Feb 08 10:28:44 AM UTC 25 335080158393 ps
T374 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_lowpower_counter.2320116839 Feb 08 10:26:26 AM UTC 25 Feb 08 10:28:45 AM UTC 25 31831851665 ps
T254 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2433551136 Feb 08 10:19:59 AM UTC 25 Feb 08 10:28:45 AM UTC 25 601226623399 ps
T59 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_fsm_reset.2950554529 Feb 08 10:20:02 AM UTC 25 Feb 08 10:28:55 AM UTC 25 70257829654 ps
T134 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_both.3013445242 Feb 08 10:21:05 AM UTC 25 Feb 08 10:29:21 AM UTC 25 495804097339 ps
T375 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled_fixed.221878965 Feb 08 10:27:10 AM UTC 25 Feb 08 10:29:11 AM UTC 25 168162035194 ps
T376 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3540058931 Feb 08 10:22:54 AM UTC 25 Feb 08 10:29:12 AM UTC 25 166792565014 ps
T275 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4259937255 Feb 08 10:19:51 AM UTC 25 Feb 08 10:29:13 AM UTC 25 424790553104 ps
T377 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_polled_fixed.1599972080 Feb 08 10:19:50 AM UTC 25 Feb 08 10:29:17 AM UTC 25 327163550317 ps
T378 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_poweron_counter.1067315987 Feb 08 10:29:12 AM UTC 25 Feb 08 10:29:19 AM UTC 25 4830298067 ps
T379 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_alert_test.2877999006 Feb 08 10:29:22 AM UTC 25 Feb 08 10:29:25 AM UTC 25 525719376 ps
T380 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_lowpower_counter.1310870458 Feb 08 10:27:41 AM UTC 25 Feb 08 10:29:27 AM UTC 25 32798992389 ps
T243 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_both.2467188177 Feb 08 10:24:33 AM UTC 25 Feb 08 10:29:33 AM UTC 25 165473796636 ps
T381 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1557366674 Feb 08 10:25:56 AM UTC 25 Feb 08 10:29:39 AM UTC 25 404495002886 ps
T382 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_smoke.2860523190 Feb 08 10:29:26 AM UTC 25 Feb 08 10:29:54 AM UTC 25 5957966921 ps
T137 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_stress_all.2111383950 Feb 08 10:20:35 AM UTC 25 Feb 08 10:29:59 AM UTC 25 341218448047 ps
T135 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_clock_gating.1560741882 Feb 08 10:26:11 AM UTC 25 Feb 08 10:30:11 AM UTC 25 363283729468 ps
T223 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_interrupt.215829645 Feb 08 10:22:45 AM UTC 25 Feb 08 10:30:19 AM UTC 25 161413112845 ps
T225 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_polled.397727725 Feb 08 10:20:18 AM UTC 25 Feb 08 10:30:31 AM UTC 25 491813553735 ps
T383 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2492967240 Feb 08 10:20:52 AM UTC 25 Feb 08 10:30:34 AM UTC 25 331300930123 ps
T51 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3649579383 Feb 08 10:26:28 AM UTC 25 Feb 08 10:30:39 AM UTC 25 468148894168 ps
T60 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_fsm_reset.1152799640 Feb 08 10:22:00 AM UTC 25 Feb 08 10:30:44 AM UTC 25 94815510914 ps
T101 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_poweron_counter.3499447640 Feb 08 10:30:32 AM UTC 25 Feb 08 10:30:51 AM UTC 25 4664389890 ps
T102 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_fsm_reset.1202373769 Feb 08 10:19:52 AM UTC 25 Feb 08 10:30:55 AM UTC 25 69946061028 ps
T103 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_alert_test.120514122 Feb 08 10:30:56 AM UTC 25 Feb 08 10:30:59 AM UTC 25 563471822 ps
T104 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_lowpower_counter.3541258494 Feb 08 10:30:35 AM UTC 25 Feb 08 10:31:09 AM UTC 25 40215557612 ps
T105 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_smoke.992561243 Feb 08 10:30:59 AM UTC 25 Feb 08 10:31:13 AM UTC 25 5856182923 ps
T106 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_polled.2542277459 Feb 08 10:27:05 AM UTC 25 Feb 08 10:31:15 AM UTC 25 164841325248 ps
T63 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_fsm_reset.217367562 Feb 08 10:20:30 AM UTC 25 Feb 08 10:31:15 AM UTC 25 76870417990 ps
T107 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_clock_gating.570361479 Feb 08 10:30:14 AM UTC 25 Feb 08 10:31:21 AM UTC 25 168122199538 ps
T384 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled_fixed.1166340793 Feb 08 10:28:16 AM UTC 25 Feb 08 10:31:24 AM UTC 25 163314877518 ps
T237 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_interrupt.2335273980 Feb 08 10:24:01 AM UTC 25 Feb 08 10:31:25 AM UTC 25 166819033445 ps
T385 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_lowpower_counter.45271631 Feb 08 10:29:13 AM UTC 25 Feb 08 10:31:41 AM UTC 25 36803472660 ps
T229 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup.3018985215 Feb 08 10:24:04 AM UTC 25 Feb 08 10:31:57 AM UTC 25 175836900689 ps
T142 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_filters_interrupt.231363993 Feb 08 10:25:27 AM UTC 25 Feb 08 10:31:58 AM UTC 25 497716387662 ps
T210 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_fsm_reset.4018468480 Feb 08 10:24:44 AM UTC 25 Feb 08 10:32:04 AM UTC 25 73501903143 ps
T386 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_poweron_counter.1992017511 Feb 08 10:31:58 AM UTC 25 Feb 08 10:32:16 AM UTC 25 4930425138 ps
T206 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/6.adc_ctrl_fsm_reset.3578472922 Feb 08 10:26:28 AM UTC 25 Feb 08 10:32:17 AM UTC 25 66700664583 ps
T52 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2082107938 Feb 08 10:30:45 AM UTC 25 Feb 08 10:32:33 AM UTC 25 134319928142 ps
T387 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_alert_test.2126656015 Feb 08 10:32:34 AM UTC 25 Feb 08 10:32:38 AM UTC 25 531063656 ps
T31 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1481003467 Feb 08 10:29:18 AM UTC 25 Feb 08 10:32:39 AM UTC 25 62702964676 ps
T388 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_smoke.3592500387 Feb 08 10:32:39 AM UTC 25 Feb 08 10:32:45 AM UTC 25 5963226774 ps
T138 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2474222171 Feb 08 10:31:15 AM UTC 25 Feb 08 10:32:52 AM UTC 25 154446316021 ps
T389 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2578433052 Feb 08 10:20:55 AM UTC 25 Feb 08 10:33:03 AM UTC 25 401417611176 ps
T268 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled.3993020834 Feb 08 10:31:10 AM UTC 25 Feb 08 10:33:06 AM UTC 25 159602262713 ps
T192 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_both.2917834473 Feb 08 10:30:21 AM UTC 25 Feb 08 10:33:27 AM UTC 25 192749198673 ps
T390 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_lowpower_counter.1899803 Feb 08 10:31:59 AM UTC 25 Feb 08 10:33:47 AM UTC 25 44028580186 ps
T166 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_polled.3781645209 Feb 08 10:32:40 AM UTC 25 Feb 08 10:34:00 AM UTC 25 329621432883 ps
T391 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4186171284 Feb 08 10:27:23 AM UTC 25 Feb 08 10:34:04 AM UTC 25 397043583983 ps
T61 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_fsm_reset.1717537394 Feb 08 10:27:42 AM UTC 25 Feb 08 10:34:10 AM UTC 25 81807912488 ps
T136 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/1.adc_ctrl_filters_both.4259047493 Feb 08 10:20:01 AM UTC 25 Feb 08 10:34:18 AM UTC 25 356957020395 ps
T392 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_poweron_counter.1760821988 Feb 08 10:34:06 AM UTC 25 Feb 08 10:34:24 AM UTC 25 5466708158 ps
T139 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup.1838674090 Feb 08 10:31:21 AM UTC 25 Feb 08 10:35:07 AM UTC 25 177162227840 ps
T202 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1189914585 Feb 08 10:27:21 AM UTC 25 Feb 08 10:35:10 AM UTC 25 490145783850 ps
T393 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_alert_test.2638927803 Feb 08 10:35:08 AM UTC 25 Feb 08 10:35:11 AM UTC 25 364586933 ps
T155 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt.3226950114 Feb 08 10:28:29 AM UTC 25 Feb 08 10:35:19 AM UTC 25 331161523226 ps
T394 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_smoke.3771469276 Feb 08 10:35:10 AM UTC 25 Feb 08 10:35:19 AM UTC 25 5902154261 ps
T238 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_interrupt.394320279 Feb 08 10:29:40 AM UTC 25 Feb 08 10:35:25 AM UTC 25 327418327896 ps
T395 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_lowpower_counter.993360036 Feb 08 10:34:11 AM UTC 25 Feb 08 10:35:29 AM UTC 25 35920934125 ps
T250 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup.2852710461 Feb 08 10:28:45 AM UTC 25 Feb 08 10:35:41 AM UTC 25 591577184997 ps
T236 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_interrupt.900036006 Feb 08 10:20:51 AM UTC 25 Feb 08 10:35:49 AM UTC 25 322940792517 ps
T167 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_both.3065142619 Feb 08 10:23:12 AM UTC 25 Feb 08 10:35:56 AM UTC 25 207846014591 ps
T396 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_interrupt_fixed.89663999 Feb 08 10:28:45 AM UTC 25 Feb 08 10:36:04 AM UTC 25 328443108992 ps
T174 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3414713202 Feb 08 10:30:11 AM UTC 25 Feb 08 10:36:04 AM UTC 25 405663307230 ps
T249 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_both.1662232172 Feb 08 10:27:38 AM UTC 25 Feb 08 10:36:05 AM UTC 25 161506232112 ps
T156 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_both.1240590086 Feb 08 10:31:43 AM UTC 25 Feb 08 10:36:08 AM UTC 25 330924632480 ps
T203 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_polled_fixed.3127026510 Feb 08 10:31:13 AM UTC 25 Feb 08 10:36:11 AM UTC 25 489894666508 ps
T397 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_poweron_counter.1661430514 Feb 08 10:36:05 AM UTC 25 Feb 08 10:36:12 AM UTC 25 4886916036 ps
T398 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_alert_test.1916667427 Feb 08 10:36:13 AM UTC 25 Feb 08 10:36:16 AM UTC 25 426340456 ps
T227 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_stress_all.3486305617 Feb 08 10:22:04 AM UTC 25 Feb 08 10:36:20 AM UTC 25 329648351042 ps
T399 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_smoke.2033130663 Feb 08 10:36:16 AM UTC 25 Feb 08 10:36:21 AM UTC 25 6352260814 ps
T400 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_lowpower_counter.3002775746 Feb 08 10:36:05 AM UTC 25 Feb 08 10:36:29 AM UTC 25 30106978962 ps
T401 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3281669711 Feb 08 10:33:03 AM UTC 25 Feb 08 10:36:41 AM UTC 25 169468722803 ps
T53 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.7872988 Feb 08 10:32:17 AM UTC 25 Feb 08 10:36:51 AM UTC 25 426581478496 ps
T157 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_interrupt.906595773 Feb 08 10:32:52 AM UTC 25 Feb 08 10:36:55 AM UTC 25 336136200016 ps
T207 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_fsm_reset.3264723166 Feb 08 10:23:29 AM UTC 25 Feb 08 10:37:05 AM UTC 25 134932778079 ps
T158 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt.1118964705 Feb 08 10:35:19 AM UTC 25 Feb 08 10:37:11 AM UTC 25 164193043782 ps
T402 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_poweron_counter.2791081708 Feb 08 10:37:06 AM UTC 25 Feb 08 10:37:17 AM UTC 25 4333996505 ps
T403 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1623122662 Feb 08 10:24:08 AM UTC 25 Feb 08 10:37:18 AM UTC 25 605723606190 ps
T255 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/2.adc_ctrl_filters_both.3037516167 Feb 08 10:20:26 AM UTC 25 Feb 08 10:37:27 AM UTC 25 327258266887 ps
T131 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3190497788 Feb 08 10:36:09 AM UTC 25 Feb 08 10:37:32 AM UTC 25 307519272015 ps
T404 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_alert_test.1766677157 Feb 08 10:37:33 AM UTC 25 Feb 08 10:37:37 AM UTC 25 488615798 ps
T228 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled.1913167114 Feb 08 10:29:28 AM UTC 25 Feb 08 10:38:00 AM UTC 25 338140744212 ps
T239 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_clock_gating.2603931543 Feb 08 10:31:26 AM UTC 25 Feb 08 10:38:02 AM UTC 25 590502239974 ps
T405 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_smoke.230559536 Feb 08 10:37:38 AM UTC 25 Feb 08 10:38:05 AM UTC 25 5956730998 ps
T269 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_filters_polled.2148766634 Feb 08 10:23:49 AM UTC 25 Feb 08 10:38:17 AM UTC 25 487002011076 ps
T294 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled.1611767948 Feb 08 10:35:12 AM UTC 25 Feb 08 10:38:20 AM UTC 25 157153178672 ps
T406 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled_fixed.715931958 Feb 08 10:36:20 AM UTC 25 Feb 08 10:38:25 AM UTC 25 163212542915 ps
T161 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.261900392 Feb 08 10:34:25 AM UTC 25 Feb 08 10:38:48 AM UTC 25 528457352244 ps
T407 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_lowpower_counter.3645792504 Feb 08 10:37:12 AM UTC 25 Feb 08 10:39:04 AM UTC 25 36394491378 ps
T408 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_poweron_counter.928618125 Feb 08 10:38:49 AM UTC 25 Feb 08 10:39:13 AM UTC 25 4985498409 ps
T143 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_interrupt.1829338151 Feb 08 10:31:15 AM UTC 25 Feb 08 10:39:30 AM UTC 25 330901927134 ps
T409 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_lowpower_counter.3807473735 Feb 08 10:39:05 AM UTC 25 Feb 08 10:39:31 AM UTC 25 31830592348 ps
T144 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_stress_all.3252154805 Feb 08 10:32:18 AM UTC 25 Feb 08 10:39:42 AM UTC 25 164904261942 ps
T410 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_alert_test.3043689563 Feb 08 10:39:42 AM UTC 25 Feb 08 10:39:45 AM UTC 25 463441806 ps
T165 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt.1695062879 Feb 08 10:36:21 AM UTC 25 Feb 08 10:39:47 AM UTC 25 496847577047 ps
T185 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_fsm_reset.2678969006 Feb 08 10:29:14 AM UTC 25 Feb 08 10:40:00 AM UTC 25 106651993292 ps
T186 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_smoke.596742193 Feb 08 10:39:46 AM UTC 25 Feb 08 10:40:03 AM UTC 25 6007342960 ps
T187 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_stress_all.1219600265 Feb 08 10:34:47 AM UTC 25 Feb 08 10:40:08 AM UTC 25 332074938113 ps
T188 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3923209386 Feb 08 10:22:57 AM UTC 25 Feb 08 10:40:10 AM UTC 25 401017513962 ps
T168 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_clock_gating.145727322 Feb 08 10:35:50 AM UTC 25 Feb 08 10:40:28 AM UTC 25 527080064850 ps
T189 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.655292033 Feb 08 10:39:31 AM UTC 25 Feb 08 10:40:42 AM UTC 25 18055766664 ps
T190 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_polled.1539955115 Feb 08 10:36:17 AM UTC 25 Feb 08 10:41:00 AM UTC 25 338511364305 ps
T145 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_clock_gating.1927381499 Feb 08 10:33:49 AM UTC 25 Feb 08 10:41:05 AM UTC 25 481669519669 ps
T191 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_fsm_reset.34127373 Feb 08 10:30:40 AM UTC 25 Feb 08 10:41:08 AM UTC 25 109138849975 ps
T241 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_clock_gating.4164437349 Feb 08 10:36:56 AM UTC 25 Feb 08 10:41:14 AM UTC 25 183118085664 ps
T411 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_poweron_counter.3858138240 Feb 08 10:41:02 AM UTC 25 Feb 08 10:41:17 AM UTC 25 3127518801 ps
T273 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_both.1630403877 Feb 08 10:38:36 AM UTC 25 Feb 08 10:41:29 AM UTC 25 157845861785 ps
T412 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3175683899 Feb 08 10:35:26 AM UTC 25 Feb 08 10:41:30 AM UTC 25 486422154352 ps
T413 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_alert_test.3047718189 Feb 08 10:41:29 AM UTC 25 Feb 08 10:41:32 AM UTC 25 422701680 ps
T414 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_smoke.1541198466 Feb 08 10:41:31 AM UTC 25 Feb 08 10:41:59 AM UTC 25 5827186648 ps
T415 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1269070795 Feb 08 10:31:25 AM UTC 25 Feb 08 10:42:14 AM UTC 25 408148646285 ps
T162 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_clock_gating.1546856993 Feb 08 10:38:26 AM UTC 25 Feb 08 10:42:18 AM UTC 25 340356048308 ps
T169 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/4.adc_ctrl_clock_gating.4270735091 Feb 08 10:23:08 AM UTC 25 Feb 08 10:42:27 AM UTC 25 545888078903 ps
T416 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_wakeup_fixed.523996196 Feb 08 10:36:53 AM UTC 25 Feb 08 10:42:43 AM UTC 25 204274515963 ps
T175 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1549524766 Feb 08 10:37:19 AM UTC 25 Feb 08 10:42:51 AM UTC 25 168175667358 ps
T226 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup.3655211872 Feb 08 10:33:07 AM UTC 25 Feb 08 10:43:13 AM UTC 25 368689180196 ps
T417 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1032962075 Feb 08 10:35:41 AM UTC 25 Feb 08 10:43:23 AM UTC 25 199716826791 ps
T418 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_lowpower_counter.1999917963 Feb 08 10:41:06 AM UTC 25 Feb 08 10:43:26 AM UTC 25 31879679726 ps
T419 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_poweron_counter.1540751009 Feb 08 10:43:24 AM UTC 25 Feb 08 10:43:28 AM UTC 25 3239133590 ps
T205 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_stress_all.3437491347 Feb 08 10:36:12 AM UTC 25 Feb 08 10:43:28 AM UTC 25 121082504001 ps
T256 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_clock_gating.3853635302 Feb 08 10:28:56 AM UTC 25 Feb 08 10:43:36 AM UTC 25 491679652307 ps
T146 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_interrupt.1274673209 Feb 08 10:40:03 AM UTC 25 Feb 08 10:43:55 AM UTC 25 327192495205 ps
T420 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_alert_test.2639562317 Feb 08 10:43:56 AM UTC 25 Feb 08 10:44:00 AM UTC 25 349865999 ps
T421 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_smoke.3656316740 Feb 08 10:44:01 AM UTC 25 Feb 08 10:44:07 AM UTC 25 5658716428 ps
T208 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/10.adc_ctrl_fsm_reset.3007132781 Feb 08 10:32:05 AM UTC 25 Feb 08 10:44:18 AM UTC 25 95237116076 ps
T317 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/7.adc_ctrl_filters_interrupt.1660353051 Feb 08 10:27:14 AM UTC 25 Feb 08 10:44:19 AM UTC 25 493863749944 ps
T422 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled_fixed.802453457 Feb 08 10:40:00 AM UTC 25 Feb 08 10:44:29 AM UTC 25 163200111856 ps
T423 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_filters_polled_fixed.1962019557 Feb 08 10:29:34 AM UTC 25 Feb 08 10:44:44 AM UTC 25 328578531829 ps
T217 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_fsm_reset.1304091856 Feb 08 10:37:18 AM UTC 25 Feb 08 10:44:59 AM UTC 25 83131676457 ps
T242 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_both.2572251235 Feb 08 10:40:44 AM UTC 25 Feb 08 10:45:03 AM UTC 25 322597631135 ps
T163 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/0.adc_ctrl_filters_both.3672547812 Feb 08 10:19:51 AM UTC 25 Feb 08 10:45:05 AM UTC 25 538098131689 ps
T424 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_poweron_counter.3981799835 Feb 08 10:45:06 AM UTC 25 Feb 08 10:45:16 AM UTC 25 3502762172 ps
T425 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3757024332 Feb 08 10:42:18 AM UTC 25 Feb 08 10:45:30 AM UTC 25 165511555111 ps
T257 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_polled.2269339783 Feb 08 10:39:47 AM UTC 25 Feb 08 10:45:37 AM UTC 25 487288478352 ps
T193 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_polled.2334780614 Feb 08 10:28:08 AM UTC 25 Feb 08 10:45:42 AM UTC 25 485102002793 ps
T426 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_lowpower_counter.1383738825 Feb 08 10:45:17 AM UTC 25 Feb 08 10:45:44 AM UTC 25 23203977221 ps
T427 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_alert_test.3130129299 Feb 08 10:45:45 AM UTC 25 Feb 08 10:45:48 AM UTC 25 514508291 ps
T234 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2396633498 Feb 08 10:43:29 AM UTC 25 Feb 08 10:45:50 AM UTC 25 134616983086 ps
T428 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_wakeup_fixed.23827542 Feb 08 10:42:44 AM UTC 25 Feb 08 10:45:52 AM UTC 25 202786499663 ps
T293 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/9.adc_ctrl_stress_all.1389895212 Feb 08 10:30:52 AM UTC 25 Feb 08 10:45:54 AM UTC 25 387765296865 ps
T147 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_clock_gating.1406457867 Feb 08 10:42:52 AM UTC 25 Feb 08 10:46:01 AM UTC 25 343690205312 ps
T429 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_smoke.587424438 Feb 08 10:45:49 AM UTC 25 Feb 08 10:46:06 AM UTC 25 6019948515 ps
T357 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_fsm_reset.572564731 Feb 08 10:34:19 AM UTC 25 Feb 08 10:46:18 AM UTC 25 123709504416 ps
T430 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_lowpower_counter.1041123646 Feb 08 10:43:27 AM UTC 25 Feb 08 10:46:20 AM UTC 25 40948492124 ps
T244 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/5.adc_ctrl_stress_all.3375265934 Feb 08 10:25:04 AM UTC 25 Feb 08 10:46:28 AM UTC 25 516005627640 ps
T431 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_fsm_reset.901780751 Feb 08 10:36:06 AM UTC 25 Feb 08 10:46:31 AM UTC 25 77856275426 ps
T432 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2913369333 Feb 08 10:40:28 AM UTC 25 Feb 08 10:46:41 AM UTC 25 187161778215 ps
T433 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_poweron_counter.1057498120 Feb 08 10:46:32 AM UTC 25 Feb 08 10:46:49 AM UTC 25 3429300747 ps
T253 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_clock_gating.1727717077 Feb 08 10:40:43 AM UTC 25 Feb 08 10:47:00 AM UTC 25 542935025311 ps
T434 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3179366228 Feb 08 10:44:20 AM UTC 25 Feb 08 10:47:15 AM UTC 25 164831733488 ps
T435 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1463184655 Feb 08 10:46:02 AM UTC 25 Feb 08 10:47:55 AM UTC 25 171347379027 ps
T436 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_alert_test.3308993409 Feb 08 10:47:56 AM UTC 25 Feb 08 10:47:59 AM UTC 25 308793342 ps
T289 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_wakeup.1103444363 Feb 08 10:46:07 AM UTC 25 Feb 08 10:48:00 AM UTC 25 175626521675 ps
T437 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_smoke.1551745272 Feb 08 10:47:59 AM UTC 25 Feb 08 10:48:05 AM UTC 25 5761313206 ps
T360 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_fsm_reset.2610788671 Feb 08 10:39:14 AM UTC 25 Feb 08 10:48:12 AM UTC 25 115873053705 ps
T438 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_filters_wakeup_fixed.757250416 Feb 08 10:28:45 AM UTC 25 Feb 08 10:48:12 AM UTC 25 607767642848 ps
T439 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_lowpower_counter.1499207878 Feb 08 10:46:42 AM UTC 25 Feb 08 10:48:16 AM UTC 25 40509552628 ps
T170 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/3.adc_ctrl_filters_wakeup.1296488023 Feb 08 10:20:55 AM UTC 25 Feb 08 10:48:17 AM UTC 25 513095555352 ps
T337 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_interrupt.1431082839 Feb 08 10:44:20 AM UTC 25 Feb 08 10:48:21 AM UTC 25 160719865089 ps
T440 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_polled_fixed.2190810713 Feb 08 10:42:00 AM UTC 25 Feb 08 10:48:29 AM UTC 25 494262689707 ps
T271 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/8.adc_ctrl_stress_all.2182810651 Feb 08 10:29:20 AM UTC 25 Feb 08 10:48:31 AM UTC 25 375782908599 ps
T281 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/17.adc_ctrl_filters_polled.2164127019 Feb 08 10:44:08 AM UTC 25 Feb 08 10:48:44 AM UTC 25 489753817884 ps
T87 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2784371457 Feb 08 10:41:15 AM UTC 25 Feb 08 10:48:54 AM UTC 25 540764176928 ps
T91 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_poweron_counter.1118627763 Feb 08 10:48:32 AM UTC 25 Feb 08 10:48:55 AM UTC 25 4228859426 ps
T92 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/15.adc_ctrl_fsm_reset.3787077298 Feb 08 10:41:09 AM UTC 25 Feb 08 10:49:08 AM UTC 25 92820200029 ps
T93 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_interrupt_fixed.266768155 Feb 08 10:38:14 AM UTC 25 Feb 08 10:49:09 AM UTC 25 321456799520 ps
T94 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_alert_test.3032831759 Feb 08 10:49:10 AM UTC 25 Feb 08 10:49:14 AM UTC 25 490185800 ps
T95 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/20.adc_ctrl_smoke.1996921529 Feb 08 10:49:14 AM UTC 25 Feb 08 10:49:21 AM UTC 25 6210894662 ps
T96 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/12.adc_ctrl_filters_polled_fixed.1772561463 Feb 08 10:35:19 AM UTC 25 Feb 08 10:49:46 AM UTC 25 495467477753 ps
T97 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/16.adc_ctrl_filters_interrupt.74759159 Feb 08 10:42:15 AM UTC 25 Feb 08 10:49:52 AM UTC 25 164284044954 ps
T98 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3303670524 Feb 08 10:33:28 AM UTC 25 Feb 08 10:50:10 AM UTC 25 402839164601 ps
T99 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/13.adc_ctrl_filters_interrupt_fixed.346927302 Feb 08 10:36:31 AM UTC 25 Feb 08 10:50:11 AM UTC 25 485119864911 ps
T441 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_lowpower_counter.64992615 Feb 08 10:48:44 AM UTC 25 Feb 08 10:50:23 AM UTC 25 43632651230 ps
T442 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/19.adc_ctrl_filters_wakeup.395475658 Feb 08 10:48:17 AM UTC 25 Feb 08 10:50:28 AM UTC 25 188539921597 ps
T443 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/18.adc_ctrl_filters_polled.974325922 Feb 08 10:45:50 AM UTC 25 Feb 08 10:50:41 AM UTC 25 328267686450 ps
T444 /workspaces/repo/scratch/os_regression/adc_ctrl-sim-vcs/coverage/default/14.adc_ctrl_filters_wakeup.1020641343 Feb 08 10:38:17 AM UTC 25 Feb 08 10:50:42 AM UTC 25 247996643037 ps
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