Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
3651 4007 91.12 3651 4007 91.12 1


Total groups in report: 16
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 11 15 73.33 100.00 1 100 1 1 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0} 11 13 84.62 1 100 1 0 64 64
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg 39 45 86.67 86.67 1 100 1 1 64 64
adc_ctrl_env_pkg::adc_ctrl_filter_cg_wrapper#(10,10)::adc_ctrl_filter_cg 213 230 92.61 90.62 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 13 14 92.86 100.00 1 100 1 1 64 64
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg 42 45 93.33 93.33 1 100 1 1 64 64
adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg 12 12 100.00 1 100 1 0 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=0} 9 9 100.00 1 100 1 0 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::req_ack_cg 3 3 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%