Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22749

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

2995

1

T9

14

T12

32

T15

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19838

1

T2

20

T3

20

T4

19

auto[1]

5906

1

T9

14

T12

56

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T219	1		-	-		-	-
values[0]	26	1			T87	2		T220	6		T221	18
values[1]	523	1			T12	30		T41	46		T137	1
values[2]	2953	1			T13	1		T16	11		T17	23
values[3]	791	1			T12	2		T56	11		T152	1
values[4]	655	1			T15	46		T49	2		T152	1
values[5]	812	1			T153	21		T134	7		T107	25
values[6]	707	1			T56	12		T159	11		T222	1
values[7]	601	1			T140	1		T141	1		T57	18
values[8]	811	1			T9	14		T14	4		T18	4
values[9]	1063	1			T12	26		T19	10		T132	12
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T12	30		T41	46		T29	3
values[1]	2789	1			T13	1		T16	11		T17	23
values[2]	825	1			T12	2		T49	3		T152	1
values[3]	841	1			T15	46		T152	1		T153	21
values[4]	697	1			T159	11		T134	7		T223	12
values[5]	746	1			T56	12		T57	18		T29	28
values[6]	660	1			T140	1		T141	1		T29	2
values[7]	653	1			T14	4		T18	4		T20	6
values[8]	854	1			T9	14		T132	12		T49	1
values[9]	103	1			T12	26		T19	10		T224	1
minimum	16823	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T142	1		T52	6		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	15		T41	25		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T13	1		T16	11		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T225	1		T168	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T49	2		T152	1		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T30	8		T167	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T15	13		T153	11		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	10		T152	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T134	5		T156	13		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T159	11		T223	1		T229	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T56	12		T29	13		T173	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T57	14		T230	1		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T141	1		T29	1		T134	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	1		T50	6		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T14	1		T18	3		T20	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T132	1		T225	1		T51	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T132	1		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	1		T30	2		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T12	13		T19	10		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T224	1		T231	1		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T219	1		T233	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T52	1		T155	2		T187	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	15		T41	21		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T17	21		T18	3		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T168	1		T234	9		T235	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	1		T154	13		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T30	2		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T15	14		T153	10		T160	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	9		T161	1		T87	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T134	2		T156	12		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T223	11		T156	2		T189	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	15		T142	2		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T57	4		T107	12		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	1		T134	2		T135	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	1		T236	22		T131	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	3		T18	1		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T132	12		T51	13		T192	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T132	11		T237	12		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	13		T238	16		T239	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T12	13		T182	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T231	16		T240	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T219	12		T233	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T87	2		T220	4		T221	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T142	1		T52	6		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	15		T41	25		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T29	2		T168	1		T241	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T56	11		T152	1		T154	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T30	8		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	13		T49	1		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T15	10		T152	1		T227	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T153	11		T134	5		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T107	13		T229	14		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T56	12		T142	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T159	11		T222	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T140	1		T141	1		T29	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T57	14		T230	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	1		T18	3		T20	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	1		T140	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	347	1			T12	13		T19	10		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T30	2		T133	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T220	2		T221	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T52	1		T155	2		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	15		T41	21		T242	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T17	21		T18	3		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	1		T168	1		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T154	13		T243	9		T135	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T30	2		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	14		T49	1		T160	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	9		T227	10		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T153	10		T134	2		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T107	12		T142	14		T157	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	2		T52	2		T53	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T223	11		T236	12		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T29	16		T134	2		T135	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T57	4		T131	1		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T14	3		T18	1		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	13		T132	12		T50	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	13		T132	11		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T238	16		T239	14		T145	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T142	1		T52	4		T155	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	16		T41	27		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T13	1		T16	1		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T225	1		T168	2		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	3		T152	1		T154	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	2		T30	7		T167	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T15	15		T153	11		T160	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	10		T152	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T134	3		T156	13		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T159	1		T223	12		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	1		T29	17		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T57	5		T230	1		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T141	1		T29	2		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T140	1		T50	5		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	4		T18	3		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T132	13		T225	1		T51	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T132	12		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	14		T30	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T12	14		T19	1		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T224	1		T231	17		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T219	13		T233	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T52	3		T163	12		T244	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	14		T41	19		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T16	10		T18	6		T56	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T234	3		T245	20		T246	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T154	9		T161	5		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	3		T167	4		T227	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	12		T153	10		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	9		T226	8		T87	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T134	4		T156	12		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T159	10		T229	13		T156	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T56	11		T29	11		T173	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T57	13		T107	12		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T134	4		T135	10		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T50	2		T248	15		T46	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T18	1		T20	5		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T51	11		T192	16		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T250	4		T131	10		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	1		T239	13		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T12	12		T19	9		T251	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T252	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T219	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T87	2		T220	4		T221	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T142	1		T52	4		T155	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	16		T41	27		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T29	2		T168	2		T241	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T56	1		T152	1		T154	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	2		T30	7		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	15		T49	2		T160	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	10		T152	1		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T153	11		T134	3		T238	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T107	13		T229	1		T142	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T56	1		T142	3		T52	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T159	1		T222	1		T223	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	1		T141	1		T29	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T57	5		T230	1		T131	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	4		T18	3		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	14		T140	1		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T12	14		T19	1		T132	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T30	1		T133	1		T225	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T220	2		T221	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T52	3		T244	9		T247	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	14		T41	19		T253	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T16	10		T18	6		T254	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T29	1		T241	19		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T56	10		T154	9		T243	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	3		T167	4		T255	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	12		T160	12		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	9		T227	3		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T153	10		T134	4		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T107	12		T229	13		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T56	11		T53	8		T244	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T159	10		T136	2		T250	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	11		T173	16		T134	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T57	13		T169	10		T256	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	1		T20	5		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T50	2		T51	11		T192	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T12	12		T19	9		T134	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	1		T239	13		T145	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22747

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

2997

1

T9

14

T12

32

T15

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19841

1

T2

20

T3

20

T4

19

auto[1]

5903

1

T9

14

T12

56

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	241	1			T12	26		T133	1		T257	1
values[1]	560	1			T12	30		T41	46		T137	1
values[2]	2871	1			T13	1		T16	11		T17	23
values[3]	843	1			T12	2		T56	11		T152	1
values[4]	576	1			T15	46		T49	2		T152	1
values[5]	943	1			T153	21		T160	27		T134	7
values[6]	657	1			T56	12		T159	11		T222	1
values[7]	639	1			T140	1		T141	1		T57	18
values[8]	805	1			T9	14		T14	4		T18	4
values[9]	808	1			T19	10		T132	12		T49	1
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	579	1			T12	30		T41	46		T29	3
values[1]	2755	1			T13	1		T16	11		T17	23
values[2]	826	1			T12	2		T49	2		T152	1
values[3]	738	1			T15	46		T152	1		T153	21
values[4]	854	1			T159	11		T160	27		T134	7
values[5]	762	1			T56	12		T57	18		T29	28
values[6]	558	1			T140	1		T141	1		T29	2
values[7]	724	1			T9	14		T14	4		T18	4
values[8]	826	1			T132	12		T49	1		T152	1
values[9]	115	1			T12	26		T19	10		T258	11
minimum	17007	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T52	6		T187	1		T163	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	15		T41	25		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T13	1		T16	11		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T225	1		T168	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T49	1		T152	1		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T30	8		T167	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	13		T153	11		T243	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	10		T152	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T160	13		T134	5		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T159	11		T223	1		T107	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T56	12		T29	13		T173	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T57	14		T230	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	1		T141	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T50	6		T236	2		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T14	1		T18	3		T20	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	1		T140	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T132	1		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T30	2		T133	1		T238	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T12	13		T19	10		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T258	1		T231	1		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16725	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T137	1		T193	1		T253	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	1		T187	14		T163	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	15		T41	21		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	919	1			T17	21		T18	3		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T168	1		T234	9		T235	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	1		T154	13		T135	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T30	2		T167	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	14		T153	10		T243	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	9		T161	1		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T160	14		T134	2		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T223	11		T107	12		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	15		T142	2		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T57	4		T142	14		T157	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	1		T134	2		T135	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T50	1		T236	22		T131	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	3		T18	1		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	13		T132	12		T51	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	11		T237	12		T131	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T238	16		T239	14		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T12	13		T182	12		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T258	9		T231	16		T240	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T253	5		T259	5		T47	11