Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19993

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

5751

1

T12

30

T13

1

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20006

1

T2

20

T3

20

T4

19

auto[1]

5738

1

T12

2

T13

1

T15

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	223	1			T154	23		T142	15		T131	2
values[0]	24	1			T305	23		T315	1		-	-
values[1]	735	1			T140	1		T49	1		T153	21
values[2]	623	1			T19	10		T20	6		T56	12
values[3]	679	1			T49	2		T50	7		T159	11
values[4]	657	1			T141	1		T132	13		T30	2
values[5]	705	1			T9	14		T18	12		T140	1
values[6]	624	1			T18	4		T152	2		T137	1
values[7]	675	1			T14	4		T15	19		T29	2
values[8]	881	1			T12	2		T15	27		T41	46
values[9]	3117	1			T12	56		T13	1		T16	11
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	668	1			T19	10		T57	18		T49	1
values[1]	2741	1			T13	1		T16	11		T17	23
values[2]	622	1			T141	1		T49	2		T50	7
values[3]	762	1			T9	14		T132	13		T230	1
values[4]	626	1			T18	12		T140	1		T29	28
values[5]	712	1			T18	4		T152	2		T137	1
values[6]	749	1			T14	4		T15	19		T29	2
values[7]	787	1			T12	28		T15	27		T41	46
values[8]	773	1			T12	30		T154	23		T133	1
values[9]	220	1			T161	9		T165	13		T256	2
minimum	17084	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	1		T30	8		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	10		T57	14		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	6		T56	12		T51	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1516	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	6		T30	2		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T141	1		T49	1		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	1		T132	1		T173	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T230	1		T31	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	9		T140	1		T29	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T107	13		T236	1		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	3		T152	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	1		T135	8		T255	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T15	10		T29	1		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T223	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	14		T56	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	13		T41	25		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T154	10		T133	1		T156	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T12	15		T160	13		T243	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T161	6		T193	1		T89	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T165	1		T256	1		T32	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16747	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T140	1		T29	2		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T30	2		T157	3		T143	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T57	4		T249	2		T255	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T51	13		T187	14		T169	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	879	1			T17	21		T151	14		T270	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	1		T136	10		T147	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T49	1		T134	2		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	13		T132	12		T238	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T31	1		T145	8		T317	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T18	3		T29	15		T239	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T107	12		T236	12		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T18	1		T167	5		T165	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T135	8		T255	2		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	9		T29	1		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	3		T223	11		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	14		T132	11		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	14		T41	21		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T154	13		T156	2		T131	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	15		T160	14		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T161	3		T89	14		T334	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T165	12		T256	1		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T41	2		T153	10		T29	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T29	1		T248	11		T197	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T154	10		T131	1		T242	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T142	1		T247	4		T32	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T305	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	1		T153	11		T30	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T140	1		T29	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	6		T56	12		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T19	10		T57	14		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T50	6		T159	11		T173	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	1		T134	5		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	1		T30	2		T225	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T141	1		T230	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T18	9		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T107	13		T236	1		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T18	3		T152	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T152	1		T255	9		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	10		T29	1		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T14	1		T135	8		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T12	1		T56	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	13		T41	25		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	13		T133	1		T156	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1739	1			T12	15		T13	1		T16	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T154	13		T131	1		T242	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T142	14		T247	1		T32	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T305	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T153	10		T30	2		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T29	1		T249	2		T87	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T51	13		T143	7		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T57	4		T134	2		T237	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	1		T136	10		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T49	1		T134	2		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	12		T238	16		T239	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	1		T131	9		T317	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	13		T18	3		T29	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T107	12		T236	12		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	1		T167	5		T165	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T255	2		T161	2		T187	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	9		T29	1		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	3		T135	8		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	1		T132	11		T192	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	14		T41	21		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	13		T156	2		T157	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1042	1			T12	15		T17	21		T151	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	1		T30	7		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	1		T57	5		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T20	1		T56	1		T51	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1190	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	5		T30	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T141	1		T49	2		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	14		T132	13		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T230	1		T31	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T18	6		T140	1		T29	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T107	13		T236	13		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T18	3		T152	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T152	1		T135	9		T255	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T15	10		T29	2		T134	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	4		T223	12		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T12	16		T56	1		T132	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	15		T41	27		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T154	14		T133	1		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T12	16		T160	15		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T161	4		T193	1		T89	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T165	13		T256	2		T32	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16876	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T140	1		T29	2		T248	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T30	3		T168	19		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T19	9		T57	13		T249	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	5		T56	11		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1205	1			T16	10		T254	32		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T50	2		T30	1		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	4		T131	10		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T173	16		T250	12		T239	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T31	1		T145	8		T289	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T18	6		T29	11		T250	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T107	12		T156	12		T147	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	1		T167	4		T47	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T135	7		T255	8		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	9		T134	13		T241	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T52	3		T136	2		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	12		T56	10		T192	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T15	12		T41	19		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T154	9		T156	1		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	14		T160	12		T243	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T161	5		T89	5		T288	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T32	1		T267	10		T335	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T153	10		T46	10		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T29	1		T248	9		T197	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T154	14		T131	2		T242	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T142	15		T247	2		T32	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T305	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	1		T153	11		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T140	1		T29	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T20	1		T56	1		T51	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	1		T57	5		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	5		T159	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T49	2		T134	3		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T132	13		T30	1		T225	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T141	1		T230	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	14		T18	6		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T107	13		T236	13		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T18	3		T152	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T152	1		T255	3		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	10		T29	2		T134	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	4		T135	9		T223	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	2		T56	1		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T15	15		T41	27		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	14		T133	1		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1386	1			T12	16		T13	1		T16	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T154	9		T89	5		T319	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T247	3		T32	1		T267	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T153	10		T30	3		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	1		T249	11		T87	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T20	5		T56	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T19	9		T57	13		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T50	2		T159	10		T173	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	4		T168	11		T170	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	1		T250	12		T239	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	1		T131	10		T289	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T18	6		T29	11		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T107	12		T156	12		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T18	1		T167	4		T47	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T255	8		T161	2		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	9		T134	13		T245	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T135	7		T52	3		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T56	10		T192	16		T53	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	12		T41	19		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	12		T156	1		T161	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1395	1			T12	14		T16	10		T160	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10