Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19694

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3274

1

T10

8

T11

2

T13

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17099

1

T2

20

T3

20

T4

1

auto[1]

5869

1

T10

8

T14

2

T15

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T243	10		T255	3		T246	2
values[0]	29	1			T262	11		T288	18		-	-
values[1]	598	1			T11	2		T19	5		T168	1
values[2]	577	1			T10	5		T16	1		T168	2
values[3]	691	1			T14	2		T15	8		T122	12
values[4]	3099	1			T18	5		T19	9		T20	28
values[5]	552	1			T42	7		T46	20		T186	6
values[6]	709	1			T120	18		T138	10		T141	3
values[7]	687	1			T13	4		T19	15		T43	11
values[8]	544	1			T39	35		T140	5		T82	3
values[9]	1213	1			T10	3		T17	1		T121	20
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	587	1			T10	5		T19	5		T141	16
values[1]	638	1			T16	1		T168	2		T183	1
values[2]	689	1			T14	2		T15	8		T19	9
values[3]	3047	1			T18	5		T20	28		T37	1
values[4]	557	1			T46	20		T120	18		T186	6
values[5]	861	1			T129	13		T45	11		T138	10
values[6]	553	1			T13	4		T19	15		T43	11
values[7]	630	1			T39	35		T82	3		T139	13
values[8]	1096	1			T10	3		T17	1		T121	20
values[9]	152	1			T243	10		T169	12		T159	17
minimum	14158	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T244	1		T124	14		T197	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	3		T19	5		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	1		T44	2		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T168	2		T183	1		T169	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T19	9		T120	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T14	1		T15	6		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T18	1		T20	28		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	6		T132	1		T80	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	15		T141	3		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T120	10		T186	6		T252	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T138	6		T236	15		T125	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T129	13		T45	8		T126	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T155	1		T140	17		T78	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	3		T19	15		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	11		T139	1		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T82	1		T142	15		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T82	1		T237	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T10	2		T17	1		T121	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T243	1		T287	12		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T169	12		T159	9		T178	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13938	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T11	1		T240	4		T262	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T244	11		T124	14		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	2		T123	11		T251	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	1		T121	12		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T292	8		T284	11		T55	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T120	8		T171	5		T281	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	1		T15	2		T173	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T18	4		T155	10		T165	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T42	1		T145	9		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	5		T247	1		T213	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T120	8		T252	20		T267	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	4		T236	12		T125	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	3		T126	15		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T155	9		T78	7		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	1		T43	2		T82	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	24		T139	12		T247	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T82	2		T128	13		T246	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T82	4		T238	10		T252	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	1		T121	18		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T243	9		T287	4		T285	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T159	8		T294	8		T338	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T11	1		T240	3		T262	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T243	1		T246	1		T287	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T255	3		T156	9		T248	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T262	1		T288	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T168	1		T29	1		T124	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	1		T19	5		T141	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T44	2		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	3		T168	2		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T153	11		T169	9		T171	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T15	6		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1781	1			T18	1		T19	9		T20	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T173	1		T132	1		T80	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	15		T155	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	6		T186	6		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T138	6		T141	3		T236	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T120	10		T252	19		T171	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	1		T140	12		T78	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	3		T19	15		T43	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T39	11		T140	5		T247	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T82	1		T142	15		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T82	1		T139	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T10	2		T17	1		T121	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T243	9		T246	1		T287	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T156	2		T248	15		T339	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T262	10		T288	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T124	14		T271	9		T267	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	1		T123	11		T240	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T44	1		T121	12		T138	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	2		T251	12		T292	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T153	10		T171	5		T281	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T15	2		T122	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T18	4		T120	8		T165	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T173	2		T145	9		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	5		T155	10		T247	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T42	1		T174	8		T248	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T138	4		T236	12		T125	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T120	8		T252	20		T171	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T155	9		T78	7		T143	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T43	2		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T39	24		T247	1		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T82	2		T128	13		T246	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T82	4		T139	12		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	1		T121	18		T138	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T244	12		T124	15		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	4		T19	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	1		T44	2		T121	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T168	2		T183	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T19	1		T120	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	2		T15	6		T173	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T18	5		T20	3		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T42	6		T132	1		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	6		T141	1		T247	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T120	9		T186	1		T252	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T138	5		T236	13		T125	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T129	1		T45	8		T126	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	10		T140	2		T78	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	4		T19	1		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	25		T139	13		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T82	3		T142	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T82	5		T237	1		T238	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T10	3		T17	1		T121	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T243	10		T287	5		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T169	1		T159	9		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14049	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T11	2		T240	4		T262	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T124	13		T197	9		T319	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	1		T19	4		T141	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	1		T151	18		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T169	12		T272	15		T156	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T19	8		T120	8		T169	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	2		T126	11		T267	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T20	25		T164	15		T167	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	1		T80	13		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T46	14		T141	2		T178	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	9		T186	5		T252	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	5		T236	14		T125	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T129	12		T45	3		T126	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T140	15		T78	9		T242	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T19	14		T43	3		T80	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T39	10		T247	1		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T142	14		T207	11		T340	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T252	11		T156	12		T158	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T138	6		T151	15		T142	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T287	11		T285	4		T310	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T169	11		T159	8		T178	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T267	9		T289	12		T341	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T240	3		T288	12		T308	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T243	10		T246	2		T287	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T255	3		T156	3		T248	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T262	11		T288	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T168	1		T29	1		T124	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	2		T19	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	1		T44	2		T121	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	4		T168	2		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T153	11		T169	1		T171	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	2		T15	6		T122	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T18	5		T19	1		T20	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T173	3		T132	1		T80	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T46	6		T155	11		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	6		T186	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T138	5		T141	1		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	9		T252	21		T171	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T155	10		T140	1		T78	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	4		T19	1		T43	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	25		T140	1		T247	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T82	3		T142	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T82	5		T139	13		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T10	3		T17	1		T121	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T287	11		T310	21		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T156	8		T248	11		T339	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T288	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T124	13		T197	9		T267	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	4		T141	15		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T44	1		T151	18		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T10	1		T251	14		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T153	10		T169	8		T171	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	2		T126	11		T55	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T19	8		T20	25		T120	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T80	13		T145	7		T171	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T46	14		T178	16		T298	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T42	1		T186	5		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T138	5		T141	2		T236	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T120	9		T252	18		T171	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T140	11		T78	9		T283	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	14		T43	3		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	10		T140	4		T247	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T142	14		T207	11		T331	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T242	2		T300	9		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T138	6		T151	15		T142	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26