Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22157

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3587

1

T12

28

T14

4

T18

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20140

1

T2

20

T3

20

T4

19

auto[1]

5604

1

T9

14

T12

2

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T170	13		T321	9		T315	5
values[0]	62	1			T225	1		T229	14		T142	1
values[1]	733	1			T14	4		T41	46		T152	1
values[2]	576	1			T222	1		T106	1		T268	1
values[3]	749	1			T141	1		T52	7		T192	26
values[4]	582	1			T9	14		T140	1		T56	12
values[5]	2841	1			T13	1		T16	11		T17	23
values[6]	622	1			T15	19		T49	1		T160	27
values[7]	793	1			T153	21		T30	12		T133	1
values[8]	661	1			T12	28		T57	18		T132	25
values[9]	1297	1			T12	30		T15	27		T18	16
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T14	4		T41	46		T152	1
values[1]	693	1			T173	17		T106	1		T268	1
values[2]	619	1			T56	12		T141	1		T49	2
values[3]	2794	1			T9	14		T13	1		T16	11
values[4]	626	1			T15	19		T19	10		T49	1
values[5]	707	1			T49	1		T153	21		T30	2
values[6]	649	1			T12	28		T30	10		T133	1
values[7]	678	1			T132	25		T152	1		T154	23
values[8]	1080	1			T12	30		T15	27		T18	16
values[9]	110	1			T50	7		T52	3		T269	1
minimum	16832	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T152	1		T225	1		T142	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T14	1		T41	25		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T106	1		T192	17		T163	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T173	17		T268	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T239	26		T269	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T56	12		T141	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1490	1			T9	1		T13	1		T16	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T140	1		T166	1		T139	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	10		T19	10		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	1		T29	2		T167	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T153	11		T30	2		T250	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T49	1		T230	1		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	8		T142	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	14		T133	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T132	1		T152	1		T154	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T132	1		T107	13		T236	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T12	15		T15	13		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T18	3		T56	11		T57	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T50	6		T269	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T52	1		T219	1		T251	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T336	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	2		T255	2		T131	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T14	3		T41	21		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T192	9		T163	8		T244	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T168	1		T234	9		T337	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T239	26		T161	3		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T49	1		T52	1		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T9	13		T17	21		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T143	11		T242	16		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T15	9		T53	24		T143	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T29	1		T167	5		T273	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T153	10		T157	6		T255	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T160	14		T134	2		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	2		T142	14		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	14		T223	11		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T132	11		T154	13		T29	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T132	12		T107	12		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	15		T15	14		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T18	1		T57	4		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T50	1		T147	1		T291	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T52	2		T251	6		T332	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T336	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T321	7		T315	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T170	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T142	1		T169	1		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T225	1		T229	14		T338	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	1		T225	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	1		T41	25		T173	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T106	1		T255	9		T163	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T222	1		T268	1		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T192	17		T239	26		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T141	1		T52	6		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T155	1		T156	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T140	1		T56	12		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T13	1		T16	11		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T49	1		T29	2		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	10		T53	16		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	1		T160	13		T243	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T153	11		T30	10		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	1		T230	1		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T132	1		T29	1		T135	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	14		T57	14		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T12	15		T15	13		T18	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T18	3		T56	11		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T321	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T169	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T338	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T142	2		T131	1		T145	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	3		T41	21		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T255	2		T163	3		T247	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T136	10		T238	16		T168	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T192	9		T239	26		T161	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T52	1		T337	12		T271	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	13		T155	2		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	1		T158	10		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T17	21		T151	14		T270	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	1		T167	5		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T15	9		T53	24		T157	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T160	14		T243	9		T51	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T153	10		T30	2		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T134	2		T223	11		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T132	11		T29	1		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	14		T57	4		T132	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	15		T15	14		T18	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T18	1		T134	2		T52	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T152	1		T225	1		T142	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T14	4		T41	27		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T106	1		T192	10		T163	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T173	1		T268	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T239	28		T269	1		T161	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T56	1		T141	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T9	14		T13	1		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T140	1		T166	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	10		T19	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T49	1		T29	2		T167	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	11		T30	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T49	1		T230	1		T160	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	7		T142	15		T155	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	16		T133	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T132	12		T152	1		T154	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T132	13		T107	13		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	16		T15	15		T18	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T18	3		T56	1		T57	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T50	5		T269	1		T147	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T52	3		T219	1		T251	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T336	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T255	8		T162	11		T169	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T41	19		T134	4		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T192	16		T163	9		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T173	16		T250	10		T234	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T239	24		T289	6		T259	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T56	11		T52	3		T309	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T16	10		T20	5		T254	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T139	15		T247	15		T259	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	9		T19	9		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	1		T167	4		T273	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T153	10		T30	1		T250	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T160	12		T134	4		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	3		T296	6		T246	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	12		T249	11		T131	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T154	9		T29	11		T135	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T107	12		T239	3		T161	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	14		T15	12		T18	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T18	1		T56	10		T57	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T50	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T251	4		T332	14		T200	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T336	16		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T321	5		T315	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T142	1		T169	2		T315	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	1		T229	1		T338	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T152	1		T225	1		T142	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	4		T41	27		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T106	1		T255	3		T163	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T222	1		T268	1		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T192	10		T239	28		T161	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T141	1		T52	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	14		T155	3		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T140	1		T56	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T13	1		T16	1		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T49	1		T29	2		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	10		T53	32		T157	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	1		T160	15		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T153	11		T30	8		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T133	1		T230	1		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	12		T29	2		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	16		T57	5		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T12	16		T15	15		T18	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T18	3		T56	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T321	4		T315	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T170	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T339	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T229	13		T338	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T162	11		T169	10		T245	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T41	19		T173	16		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T255	8		T163	6		T247	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	8		T234	3		T170	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T192	16		T239	24		T163	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T52	3		T139	15		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T156	1		T163	12		T340	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	11		T259	5		T341	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T16	10		T19	9		T20	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	1		T167	4		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	9		T53	8		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T160	12		T243	10		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T153	10		T30	4		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T134	4		T249	11		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T135	7		T271	7		T246	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	12		T57	13		T107	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	14		T15	12		T18	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T18	1		T56	10		T159	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10