Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19577

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3391

1

T10

3

T14

2

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16779

1

T2

20

T3

20

T5

10

auto[1]

6189

1

T4

1

T10

5

T11

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	312	1			T4	1		T42	2		T52	1
values[0]	58	1			T43	11		T80	11		T141	16
values[1]	709	1			T173	3		T121	13		T138	10
values[2]	3084	1			T11	2		T18	5		T20	28
values[3]	665	1			T17	1		T44	3		T80	8
values[4]	473	1			T10	5		T19	5		T186	6
values[5]	922	1			T42	7		T120	17		T168	1
values[6]	811	1			T10	3		T16	1		T19	15
values[7]	612	1			T14	2		T15	8		T155	11
values[8]	675	1			T19	9		T183	1		T140	12
values[9]	909	1			T13	4		T168	2		T129	13
minimum	13738	1			T2	20		T3	20		T5	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	901	1			T173	3		T43	11		T121	13
values[1]	3085	1			T11	2		T18	5		T20	28
values[2]	544	1			T10	5		T17	1		T19	5
values[3]	679	1			T42	7		T186	6		T137	1
values[4]	737	1			T16	1		T39	35		T120	17
values[5]	879	1			T10	3		T19	15		T46	20
values[6]	638	1			T14	2		T15	8		T155	11
values[7]	657	1			T19	9		T168	1		T183	1
values[8]	675	1			T13	4		T168	1		T129	13
values[9]	134	1			T237	1		T241	1		T245	1
minimum	14039	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T173	1		T43	9		T141	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T121	1		T80	11		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T11	1		T18	1		T20	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T151	16		T247	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	3		T19	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T17	1		T78	10		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T137	1		T82	1		T144	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T42	6		T186	6		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T39	11		T120	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T140	5		T151	5		T242	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T19	15		T46	15		T118	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T10	2		T120	10		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T122	1		T125	9		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T15	6		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T168	1		T183	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T19	9		T82	10		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	3		T129	13		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T168	1		T82	1		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T245	1		T201	12		T267	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T237	1		T241	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13899	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T293	1		T342	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T173	2		T43	2		T300	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T121	12		T138	4		T143	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T11	1		T18	4		T165	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T151	10		T247	1		T126	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	2		T44	1		T251	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T78	7		T244	11		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T82	4		T213	1		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T42	1		T121	7		T123	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T39	24		T120	8		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T242	2		T252	20		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	5		T118	9		T252	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T120	8		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	11		T125	7		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T15	2		T155	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T236	12		T127	10		T246	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T82	15		T124	1		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	1		T138	1		T128	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T82	2		T243	9		T126	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T201	1		T267	2		T343	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T175	6		T326	5		T344	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T293	13		T342	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T4	1		T42	2		T52	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T298	11		T345	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T43	9		T141	16		T279	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T80	11		T266	2		T277	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T173	1		T300	10		T55	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T121	1		T138	6		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1712	1			T11	1		T18	1		T20	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T247	1		T256	1		T126	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	2		T80	8		T251	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T17	1		T244	1		T151	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	3		T19	5		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T186	6		T78	10		T123	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T120	9		T168	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T42	6		T140	5		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	1		T19	15		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T10	2		T120	10		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T118	15		T125	9		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	1		T15	6		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T183	1		T132	1		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	9		T140	12		T82	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	3		T168	1		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T168	1		T82	1		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13620	1			T2	20		T3	20		T5	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T298	10		T345	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T43	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T277	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T173	2		T300	8		T55	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T121	12		T138	4		T143	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T11	1		T18	4		T165	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T247	1		T126	15		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	1		T251	12		T125	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T244	11		T151	10		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	2		T82	4		T213	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T78	7		T123	8		T124	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T120	8		T151	15		T152	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	1		T121	7		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T39	24		T46	5		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T120	8		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T118	9		T125	7		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	1		T15	2		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T122	11		T236	12		T171	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T82	15		T124	1		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T138	1		T128	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T82	2		T243	9		T126	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T173	3		T43	8		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T121	13		T80	1		T138	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T11	2		T18	5		T20	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T151	11		T247	2		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	4		T19	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T17	1		T78	8		T244	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T137	1		T82	5		T144	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T42	6		T186	1		T121	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T16	1		T39	25		T120	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T140	1		T151	1		T242	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T19	1		T46	6		T118	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	3		T120	9		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T122	12		T125	8		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	2		T15	6		T155	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T168	1		T183	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	1		T82	16		T124	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	4		T129	1		T138	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T168	1		T82	3		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T245	1		T201	2		T267	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T237	1		T241	1		T175	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14017	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T293	14		T342	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T43	3		T141	15		T300	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T80	10		T138	5		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T20	25		T164	15		T167	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T151	15		T126	14		T248	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	1		T19	4		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T78	9		T124	13		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T169	12		T156	8		T309	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	1		T186	5		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	10		T120	8		T151	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	4		T151	4		T242	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	14		T46	14		T118	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T120	9		T138	6		T197	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T125	8		T145	7		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	2		T140	11		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T80	13		T236	14		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	8		T82	9		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T129	12		T272	15		T332	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T126	11		T171	4		T283	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T201	11		T267	7		T333	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T346	9		T326	7		T344	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T4	1		T42	2		T52	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T298	11		T345	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T43	8		T141	1		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T80	1		T266	1		T277	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T173	3		T300	9		T55	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T121	13		T138	5		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T11	2		T18	5		T20	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T247	2		T256	1		T126	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T44	2		T80	1		T251	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T17	1		T244	12		T151	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	4		T19	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T186	1		T78	8		T123	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T120	9		T168	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T42	6		T140	1		T121	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T16	1		T19	1		T39	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	3		T120	9		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T118	10		T125	8		T237	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T14	2		T15	6		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T183	1		T132	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	1		T140	1		T82	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	4		T168	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T168	1		T82	3		T243	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13738	1			T2	20		T3	20		T5	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T298	10		T345	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T43	3		T141	15		T279	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T80	10		T266	1		T277	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T300	9		T55	2		T347	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T138	5		T141	2		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T20	25		T164	15		T167	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T126	14		T248	1		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	1		T80	7		T251	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T151	15		T124	13		T247	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	1		T19	4		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T186	5		T78	9		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T120	8		T151	18		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T42	1		T140	4		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T19	14		T39	10		T46	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T120	9		T197	21		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T118	14		T125	8		T127	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	2		T138	6		T123	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T80	13		T236	14		T169	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	8		T140	11		T82	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T129	12		T272	15		T201	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T197	9		T126	11		T171	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26