Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22101

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3643

1

T12

2

T14

4

T18

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20003

1

T2

20

T3

20

T4

19

auto[1]

5741

1

T9

14

T12

58

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T18	16		T56	11		T50	7
values[0]	35	1			T225	1		T142	4		T338	29
values[1]	760	1			T14	4		T41	46		T152	1
values[2]	622	1			T222	1		T134	7		T106	1
values[3]	698	1			T141	1		T52	7		T192	26
values[4]	575	1			T9	14		T140	1		T56	12
values[5]	2910	1			T13	1		T16	11		T17	23
values[6]	637	1			T15	19		T49	1		T30	2
values[7]	737	1			T12	26		T153	21		T30	10
values[8]	680	1			T12	2		T57	18		T132	25
values[9]	1027	1			T12	30		T15	27		T140	1
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T14	4		T41	46		T222	1
values[1]	607	1			T106	1		T268	1		T192	26
values[2]	671	1			T56	12		T141	1		T49	2
values[3]	2772	1			T9	14		T13	1		T16	11
values[4]	698	1			T19	10		T49	1		T29	3
values[5]	633	1			T15	19		T49	1		T153	21
values[6]	699	1			T12	28		T132	12		T30	10
values[7]	740	1			T57	18		T132	13		T152	1
values[8]	975	1			T12	30		T15	27		T18	16
values[9]	130	1			T50	7		T52	3		T147	2
minimum	16993	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T222	1		T142	1		T255	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	1		T41	25		T173	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T192	17		T163	4		T291	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T106	1		T268	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T141	1		T239	26		T269	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T56	12		T49	1		T52	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T9	1		T13	1		T16	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T20	6		T140	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	10		T29	2		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T49	1		T167	5		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T15	10		T153	11		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T49	1		T230	1		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	13		T132	1		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	1		T133	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T152	1		T29	14		T135	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T57	14		T132	1		T154	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	15		T15	13		T18	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T18	3		T56	11		T159	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T50	6		T291	1		T200	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T52	1		T147	1		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16716	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T225	1		T136	3		T227	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T255	2		T165	4		T162	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	3		T41	21		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T192	9		T163	5		T291	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T168	1		T146	11		T234	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T239	26		T161	3		T165	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T49	1		T52	1		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T9	13		T17	21		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T143	11		T242	16		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T29	1		T53	24		T175	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T167	5		T156	12		T143	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	9		T153	10		T157	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T160	14		T134	2		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	13		T132	11		T30	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T223	11		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	16		T135	8		T107	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	4		T132	12		T154	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	15		T15	14		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T18	1		T134	2		T161	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T50	1		T291	7		T200	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T52	2		T147	1		T172	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T227	10		T258	9		T342	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T18	9		T50	6		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T18	3		T56	11		T145	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T142	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	1		T338	15		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T152	1		T131	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	1		T41	25		T173	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T222	1		T255	9		T163	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T134	5		T106	1		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T141	1		T192	17		T239	26
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	6		T166	1		T139	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T9	1		T155	1		T156	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	1		T56	12		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T13	1		T16	11		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T20	6		T49	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	10		T30	2		T250	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	1		T160	13		T243	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	13		T153	11		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T133	1		T230	1		T134	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T132	1		T29	1		T135	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T57	14		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	15		T15	13		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T154	10		T159	11		T134	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T18	3		T50	1		T253	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T18	1		T145	8		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T142	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T338	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	1		T165	4		T162	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	3		T41	21		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T255	2		T163	8		T247	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T134	2		T136	10		T238	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T192	9		T239	26		T161	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T52	1		T168	1		T337	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	13		T155	2		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	1		T158	10		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	883	1			T17	21		T151	14		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T167	5		T143	7		T273	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T15	9		T157	6		T255	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T160	14		T243	9		T51	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	13		T153	10		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	2		T223	11		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T132	11		T29	1		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T57	4		T132	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	15		T15	14		T29	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T154	13		T134	2		T52	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T222	1		T142	1		T255	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	4		T41	27		T173	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T192	10		T163	6		T291	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T106	1		T268	1		T166	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T141	1		T239	28		T269	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T56	1		T49	2		T52	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T9	14		T13	1		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T20	1		T140	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T19	1		T29	2		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T49	1		T167	6		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	10		T153	11		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	1		T230	1		T160	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	14		T132	12		T30	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	2		T133	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T152	1		T29	19		T135	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T57	5		T132	13		T154	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	16		T15	15		T18	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T18	3		T56	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T50	5		T291	8		T200	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T52	3		T147	2		T172	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16845	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T225	1		T136	1		T227	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T255	8		T162	11		T163	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T41	19		T173	16		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T192	16		T163	3		T291	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T250	10		T234	3		T244	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T239	24		T289	6		T259	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T56	11		T52	3		T309	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T16	10		T254	32		T275	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T20	5		T139	15		T163	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T19	9		T29	1		T53	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	4		T156	12		T273	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	9		T153	10		T30	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	12		T134	4		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	12		T30	3		T296	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T249	11		T131	10		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	11		T135	7		T107	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T57	13		T154	9		T239	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	14		T15	12		T18	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T18	1		T56	10		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T50	2		T200	10		T315	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T251	4		T332	14		T184	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T64	13		T33	7		T343	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T136	2		T227	3		T292	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T18	6		T50	5		T225	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T18	3		T56	1		T145	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T142	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T225	1		T338	15		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T152	1		T131	2		T165	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	4		T41	27		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T222	1		T255	3		T163	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	3		T106	1		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T141	1		T192	10		T239	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T52	4		T166	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	14		T155	3		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T140	1		T56	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T13	1		T16	1		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T20	1		T49	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T15	10		T30	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T49	1		T160	15		T243	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	14		T153	11		T30	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T133	1		T230	1		T134	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T132	12		T29	2		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	2		T57	5		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	16		T15	15		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T154	14		T159	1		T134	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T18	6		T50	2		T253	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T18	1		T56	10		T145	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T338	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T162	11		T245	22		T267	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T41	19		T173	16		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T255	8		T163	9		T247	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T134	4		T136	8		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T192	16		T239	24		T289	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T52	3		T139	15		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T156	1		T340	3		T276	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T56	11		T163	12		T259	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T16	10		T19	9		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	5		T167	4		T273	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T15	9		T30	1		T250	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T160	12		T243	10		T51	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	12		T153	10		T30	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	4		T249	11		T131	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	7		T107	12		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T57	13		T239	3		T161	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	14		T15	12		T29	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T154	9		T159	10		T134	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10