Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19677

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3291

1

T10

3

T13

4

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16736

1

T2

20

T3

20

T5

10

auto[1]

6232

1

T4

1

T10

8

T11

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	457	1			T4	1		T42	2		T52	1
values[0]	34	1			T80	11		T141	16		T279	7
values[1]	738	1			T173	3		T43	11		T121	13
values[2]	3064	1			T11	2		T18	5		T20	28
values[3]	643	1			T17	1		T19	5		T44	3
values[4]	516	1			T10	5		T186	6		T137	1
values[5]	959	1			T39	35		T42	7		T120	17
values[6]	737	1			T10	3		T16	1		T19	15
values[7]	621	1			T14	2		T15	8		T155	11
values[8]	701	1			T19	9		T183	1		T140	12
values[9]	760	1			T13	4		T168	2		T129	13
minimum	13738	1			T2	20		T3	20		T5	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	702	1			T121	13		T138	10		T141	3
values[1]	3026	1			T11	2		T18	5		T20	28
values[2]	597	1			T10	5		T17	1		T19	5
values[3]	602	1			T42	7		T186	6		T137	1
values[4]	801	1			T16	1		T39	35		T120	35
values[5]	907	1			T10	3		T19	15		T46	20
values[6]	588	1			T14	2		T15	8		T155	11
values[7]	698	1			T19	9		T168	1		T183	1
values[8]	746	1			T13	4		T168	1		T129	13
values[9]	41	1			T237	1		T241	1		T267	10
minimum	14260	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T121	1		T281	16		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T138	6		T141	3		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1716	1			T11	1		T18	1		T20	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T45	8		T151	16		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T10	3		T19	5		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	1		T251	15		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T124	1		T144	1		T272	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T42	6		T186	6		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T16	1		T120	19		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T39	11		T140	5		T151	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T19	15		T118	15		T252	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	2		T46	15		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T14	1		T121	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	6		T155	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T168	1		T183	1		T80	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T19	9		T132	1		T82	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T138	1		T237	1		T272	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T168	1		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T267	8		T253	1		T348	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T237	1		T241	1		T349	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14004	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T80	11		T143	1		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T121	12		T281	13		T291	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	4		T242	2		T145	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T11	1		T18	4		T165	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T45	3		T151	10		T247	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	2		T44	1		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T251	12		T171	9		T271	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	1		T156	2		T309	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	1		T121	7		T78	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T120	16		T151	15		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T39	24		T242	2		T252	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T118	9		T252	10		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	1		T46	5		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	1		T121	11		T122	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	2		T155	10		T238	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T236	12		T242	8		T239	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T82	15		T124	1		T271	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T138	1		T126	13		T246	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	1		T82	2		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T267	2		T350	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T349	1		T326	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T143	15		T257	2		T300	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T4	1		T42	2		T52	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T351	1		T349	3		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T141	16		T279	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T80	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T173	1		T43	9		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	6		T141	3		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T11	1		T18	1		T20	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T45	8		T247	1		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T19	5		T44	2		T80	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	1		T151	16		T251	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	3		T124	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T186	6		T137	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T120	9		T168	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T39	11		T42	6		T140	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	1		T19	15		T120	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	2		T46	15		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	1		T118	15		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	6		T155	1		T138	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T183	1		T80	14		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	9		T140	12		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T168	1		T138	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T13	3		T168	1		T129	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13620	1			T2	20		T3	20		T5	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T126	13		T267	2		T274	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T351	11		T349	1		T326	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T173	2		T43	2		T121	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	4		T143	15		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T11	1		T18	4		T165	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	3		T247	1		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	1		T244	11		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T151	10		T251	12		T171	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	2		T124	1		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T121	7		T78	7		T82	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T120	8		T151	15		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T39	24		T42	1		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T120	8		T121	11		T145	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T46	5		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T14	1		T118	9		T123	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	2		T155	10		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T122	11		T236	12		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T82	15		T124	1		T238	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	1		T239	1		T246	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	1		T82	2		T243	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T121	13		T281	14		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T138	5		T141	1		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T11	2		T18	5		T20	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T45	8		T151	11		T247	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	4		T19	1		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T251	13		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T124	2		T144	1		T272	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T42	6		T186	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	1		T120	18		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T39	25		T140	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	1		T118	10		T252	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	3		T46	6		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	2		T121	12		T122	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T15	6		T155	11		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T168	1		T183	1		T80	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T19	1		T132	1		T82	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T138	2		T237	1		T272	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	4		T168	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T267	3		T253	1		T348	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T237	1		T241	1		T349	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14080	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T80	1		T143	16		T257	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T281	15		T347	9		T291	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T138	5		T141	2		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T20	25		T164	15		T167	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T45	3		T151	15		T213	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	1		T19	4		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T251	14		T146	7		T171	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T127	7		T156	8		T309	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T42	1		T186	5		T78	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T120	17		T151	18		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	10		T140	4		T151	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T19	14		T118	14		T252	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T46	14		T138	6		T197	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T123	9		T125	8		T171	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T15	2		T140	11		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T80	13		T236	14		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	8		T82	9		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T272	15		T126	11		T332	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T129	12		T171	4		T283	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T267	7		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T349	1		T326	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T43	3		T141	15		T253	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T80	10		T300	9		T270	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T4	1		T42	2		T52	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T351	12		T349	3		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T141	1		T279	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T80	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T173	3		T43	8		T121	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T138	5		T141	1		T143	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1390	1			T11	2		T18	5		T20	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	8		T247	2		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T19	1		T44	2		T80	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T151	11		T251	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	4		T124	2		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T186	1		T137	1		T121	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T120	9		T168	1		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T39	25		T42	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T16	1		T19	1		T120	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	3		T46	6		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	2		T118	10		T123	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	6		T155	11		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T183	1		T80	1		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	1		T140	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T168	1		T138	2		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	4		T168	1		T129	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13738	1			T2	20		T3	20		T5	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T126	11		T267	7		T274	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T349	1		T326	7		T352	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T141	15		T279	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T80	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T43	3		T281	15		T253	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T138	5		T141	2		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T20	25		T164	15		T167	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	3		T213	6		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T19	4		T44	1		T80	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T151	15		T251	14		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	1		T127	7		T156	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T186	5		T78	9		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T120	8		T151	18		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T39	10		T42	1		T140	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T19	14		T120	9		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	14		T197	21		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T118	14		T123	9		T125	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T15	2		T138	6		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T80	13		T236	14		T242	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	8		T140	11		T82	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T272	15		T332	1		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T129	12		T197	9		T169	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26