Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22281

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3463

1

T12

28

T14

4

T15

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19551

1

T2

20

T3

20

T4

19

auto[1]

6193

1

T9

14

T12

28

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	439	1			T18	4		T29	3		T30	3
values[0]	36	1			T159	11		T137	1		T161	9
values[1]	478	1			T140	1		T152	1		T29	2
values[2]	2855	1			T13	1		T16	11		T17	23
values[3]	678	1			T9	14		T57	18		T132	12
values[4]	722	1			T14	4		T15	19		T41	46
values[5]	872	1			T12	26		T15	27		T56	12
values[6]	785	1			T18	12		T20	6		T49	1
values[7]	697	1			T140	1		T141	1		T132	13
values[8]	670	1			T12	30		T19	10		T50	7
values[9]	1125	1			T12	2		T18	4		T133	1
minimum	16387	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T140	1		T152	1		T29	2
values[1]	2803	1			T9	14		T13	1		T16	11
values[2]	688	1			T57	18		T132	12		T142	3
values[3]	686	1			T14	4		T15	19		T41	46
values[4]	818	1			T15	27		T18	12		T49	1
values[5]	892	1			T12	26		T20	6		T140	1
values[6]	535	1			T141	1		T132	13		T49	2
values[7]	852	1			T237	13		T52	10		T192	26
values[8]	686	1			T12	32		T19	10		T50	7
values[9]	223	1			T18	4		T29	3		T243	20
minimum	16813	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T152	1		T159	11		T134	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T140	1		T29	1		T30	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T9	1		T13	1		T16	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T56	11		T49	1		T241	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T142	1		T268	1		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T57	14		T132	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	10		T41	25		T56	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T222	1		T250	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	1		T152	2		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	13		T18	9		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	1		T230	1		T160	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	13		T20	6		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	13		T173	17		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	1		T132	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T155	1		T227	4		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T237	1		T52	7		T192	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	15		T50	6		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T19	10		T225	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T29	2		T243	11		T169	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T18	3		T229	14		T64	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16671	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T137	1		T281	1		T321	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	2		T273	8		T247	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	1		T30	2		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T9	13		T17	21		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T241	15		T253	14		T89	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T142	2		T236	12		T161	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T57	4		T132	11		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	9		T41	21		T134	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	3		T131	9		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	16		T51	13		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	14		T18	3		T161	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T160	14		T167	5		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	13		T239	12		T169	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T29	15		T249	2		T53	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T132	12		T49	1		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T155	2		T227	10		T161	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T237	12		T52	3		T192	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	15		T50	1		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T165	4		T145	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T29	1		T243	9		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T18	1		T64	10		T279	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T321	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T18	4		T29	2		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T247	4		T344	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T159	11		T213	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T137	1		T161	6		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T152	1		T134	5		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T140	1		T29	1		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	11		T236	1		T241	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T154	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T57	14		T132	1		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T15	10		T41	25		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	1		T222	1		T250	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T56	12		T152	2		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	13		T15	13		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T49	1		T230	1		T135	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	9		T20	6		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T140	1		T29	13		T173	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T141	1		T132	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	15		T50	6		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	10		T237	1		T52	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T133	1		T243	11		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T12	1		T18	3		T225	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16256	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T29	1		T256	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T247	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T213	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T161	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T134	2		T273	8		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	1		T30	2		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T17	21		T151	14		T270	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T236	10		T241	15		T169	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	13		T154	13		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T57	4		T132	11		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T15	9		T41	21		T134	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	3		T131	9		T165	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T160	14		T135	8		T51	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	13		T15	14		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T135	8		T249	2		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T18	3		T239	12		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	15		T167	5		T53	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	12		T49	1		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	15		T50	1		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T237	12		T52	3		T238	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T243	9		T169	12		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T12	1		T18	1		T192	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T152	1		T159	1		T134	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T140	1		T29	2		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T9	14		T13	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T56	1		T49	1		T241	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T142	3		T268	1		T236	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T57	5		T132	12		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T15	10		T41	27		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	4		T222	1		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T152	2		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T15	15		T18	6		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T140	1		T230	1		T160	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	14		T20	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	17		T173	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T141	1		T132	13		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T155	3		T227	11		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T237	13		T52	7		T192	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	16		T50	5		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	2		T19	1		T225	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T29	2		T243	10		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T18	3		T229	1		T64	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16802	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T137	1		T281	1		T321	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T159	10		T134	4		T250	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T30	3		T134	13		T107	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T16	10		T154	9		T254	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T56	10		T241	19		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T161	2		T187	14		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T57	13		T274	2		T263	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	9		T41	19		T56	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T250	10		T131	10		T162	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	1		T135	17		T51	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	12		T18	6		T244	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T160	12		T167	4		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T12	12		T20	5		T239	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T29	11		T173	16		T249	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T153	10		T255	8		T291	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T227	3		T87	15		T299	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T52	3		T192	16		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	14		T50	2		T253	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	9		T139	15		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T29	1		T243	10		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T18	1		T229	13		T64	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T321	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	418	1			T18	4		T29	2		T30	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T247	2		T344	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T159	1		T213	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T137	1		T161	4		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T152	1		T134	3		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	1		T29	2		T30	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T56	1		T236	11		T241	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	14		T154	14		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T57	5		T132	12		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	10		T41	27		T134	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T222	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T56	1		T152	2		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	14		T15	15		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	1		T230	1		T135	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T18	6		T20	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T140	1		T29	17		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T141	1		T132	13		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T12	16		T50	5		T223	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	1		T237	13		T52	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T133	1		T243	10		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T12	2		T18	3		T225	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16387	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T29	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T247	3		T344	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T159	10		T213	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T161	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T134	4		T273	6		T247	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T30	3		T134	13		T107	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T16	10		T254	32		T275	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T56	10		T241	19		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T154	9		T161	2		T168	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T57	13		T274	2		T299	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	9		T41	19		T134	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T250	10		T131	10		T162	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T56	11		T30	1		T160	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	12		T15	12		T163	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	10		T249	11		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T18	6		T20	5		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T29	11		T173	16		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T153	10		T244	14		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	14		T50	2		T227	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T19	9		T52	3		T255	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T243	10		T169	10		T147	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T18	1		T229	13		T192	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10