Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22570

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3174

1

T12

28

T14

4

T15

46

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19914

1

T2

20

T3

20

T4

19

auto[1]

5830

1

T12

28

T13

1

T14

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	165	1			T49	1		T143	12		T189	5
values[0]	52	1			T239	28		T296	13		T263	9
values[1]	641	1			T140	1		T225	2		T52	7
values[2]	569	1			T49	1		T29	3		T134	16
values[3]	703	1			T19	10		T57	18		T29	2
values[4]	656	1			T12	30		T18	12		T152	1
values[5]	812	1			T18	4		T56	11		T152	2
values[6]	895	1			T12	26		T41	46		T140	1
values[7]	767	1			T9	14		T15	27		T132	13
values[8]	756	1			T12	2		T14	4		T15	19
values[9]	2927	1			T13	1		T16	11		T17	23
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	636	1			T225	1		T192	26		T238	17
values[1]	573	1			T49	1		T29	3		T134	16
values[2]	725	1			T19	10		T57	18		T29	2
values[3]	652	1			T12	30		T18	12		T152	1
values[4]	875	1			T12	26		T18	4		T41	46
values[5]	837	1			T15	27		T140	1		T132	12
values[6]	2857	1			T9	14		T13	1		T14	4
values[7]	816	1			T12	2		T15	19		T134	7
values[8]	696	1			T20	6		T56	12		T154	23
values[9]	75	1			T49	1		T189	5		T264	3
minimum	17002	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T225	1		T192	17		T238	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T131	15		T161	1		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	1		T29	2		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T136	9		T156	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T19	10		T57	14		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	1		T173	17		T135	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	15		T18	9		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T152	1		T159	11		T255	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T18	3		T56	11		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	13		T41	25		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T140	1		T132	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	13		T30	2		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T9	1		T13	1		T16	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	1		T132	1		T29	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T134	5		T190	1		T257	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	1		T15	10		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T154	10		T142	1		T53	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	6		T56	12		T107	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T49	1		T310	10		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T189	4		T264	3		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16723	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T225	1		T52	6		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T192	9		T238	16		T239	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T131	9		T161	3		T145	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T29	1		T134	2		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T136	10		T156	2		T227	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T57	4		T236	12		T241	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	1		T135	8		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	15		T18	3		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T255	6		T87	16		T259	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T18	1		T49	1		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	13		T41	21		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T132	11		T134	2		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T15	14		T135	8		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T9	13		T17	21		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	3		T132	12		T29	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T134	2		T248	14		T176	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T15	9		T131	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T154	13		T53	24		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T107	12		T237	12		T161	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T305	11		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T189	1		T307	1		T345	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T52	1		T157	3		T46	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T49	1		T169	1		T262	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T143	1		T189	4		T264	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T239	14		T263	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	7		T301	1		T346	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T140	1		T225	1		T192	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T225	1		T52	6		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	1		T29	2		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T136	9		T156	2		T227	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T19	10		T57	14		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	1		T173	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	15		T18	9		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T152	1		T250	11		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T18	3		T56	11		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T30	8		T159	11		T255	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T140	1		T132	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	13		T41	25		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T51	16		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T15	13		T132	1		T29	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T134	5		T228	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T14	1		T15	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T13	1		T16	11		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T20	6		T56	12		T107	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T169	1		T262	11		T347	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T143	11		T189	1		T307	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T239	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T296	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T192	9		T238	16		T168	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T52	1		T157	3		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	1		T134	2		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T136	10		T156	2		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T57	4		T142	14		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	1		T135	8		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	15		T18	3		T155	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T259	16		T258	4		T348	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	1		T153	10		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	2		T255	6		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T132	11		T49	1		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	13		T41	21		T155	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	13		T51	13		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	14		T132	12		T29	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T134	2		T145	8		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T14	3		T15	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T17	21		T151	14		T154	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T107	12		T237	12		T161	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T225	1		T192	10		T238	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T131	14		T161	4		T145	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	1		T29	2		T134	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	1		T136	11		T156	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T19	1		T57	5		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T29	2		T173	1		T135	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	16		T18	6		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	1		T159	1		T255	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T18	3		T56	1		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	14		T41	27		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T140	1		T132	12		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	15		T30	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T9	14		T13	1		T16	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	4		T132	13		T29	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T134	3		T190	1		T257	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	2		T15	10		T131	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T154	14		T142	1		T53	32
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	1		T56	1		T107	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T49	1		T310	1		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T189	4		T264	1		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16872	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T225	1		T52	4		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T192	16		T239	13		T175	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T131	10		T234	3		T247	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	1		T134	13		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T136	8		T156	1		T227	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T19	9		T57	13		T250	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T173	16		T135	10		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	14		T18	6		T249	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T159	10		T255	13		T87	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T18	1		T56	10		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	12		T41	19		T30	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T134	4		T167	4		T246	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T15	12		T30	1		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T16	10		T254	32		T275	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	11		T243	10		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T134	4		T248	15		T309	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T15	9		T239	11		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T154	9		T53	8		T273	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T20	5		T56	11		T107	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T310	9		T305	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	1		T264	2		T177	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T162	8		T163	6		T263	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T52	3		T46	10		T47	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T49	1		T169	2		T262	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T143	12		T189	4		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T239	15		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T296	7		T301	1		T346	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T140	1		T225	1		T192	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T225	1		T52	4		T157	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T29	2		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	11		T156	3		T227	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T19	1		T57	5		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T29	2		T173	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	16		T18	6		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T152	1		T250	1		T293	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	3		T56	1		T152	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	7		T159	1		T255	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T140	1		T132	12		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	14		T41	27		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	14		T51	18		T238	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	15		T132	13		T29	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T134	3		T228	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	2		T14	4		T15	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T13	1		T16	1		T17	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	1		T56	1		T107	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T262	14		T310	9		T347	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T189	1		T264	2		T179	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T239	13		T263	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T296	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T192	16		T162	8		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T52	3		T234	3		T247	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	1		T134	13		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T136	8		T156	1		T227	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T19	9		T57	13		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T173	16		T135	10		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	14		T18	6		T249	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T250	10		T259	16		T246	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	1		T56	10		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T30	3		T159	10		T255	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T160	12		T134	4		T250	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	12		T41	19		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T51	11		T145	2		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	12		T29	11		T135	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T134	4		T145	8		T248	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	9		T243	10		T139	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T16	10		T154	9		T254	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T20	5		T56	11		T107	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10