Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22557

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3187

1

T12

58

T15

27

T18

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19604

1

T2

20

T3

20

T4

19

auto[1]

6140

1

T9

14

T12

56

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	234	1			T52	7		T250	5		T227	1
values[0]	95	1			T256	2		T89	21		T267	19
values[1]	780	1			T19	10		T56	11		T57	18
values[2]	742	1			T9	14		T18	12		T49	1
values[3]	598	1			T140	1		T153	21		T137	1
values[4]	646	1			T15	27		T132	13		T49	1
values[5]	604	1			T12	56		T152	2		T29	2
values[6]	672	1			T20	6		T56	12		T132	12
values[7]	761	1			T222	1		T135	19		T225	1
values[8]	2865	1			T13	1		T14	4		T15	19
values[9]	946	1			T12	2		T41	46		T29	28
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	758	1			T19	10		T56	11		T49	2
values[1]	758	1			T9	14		T18	12		T49	1
values[2]	503	1			T140	1		T132	13		T153	21
values[3]	827	1			T12	30		T15	27		T49	1
values[4]	488	1			T12	26		T132	12		T29	2
values[5]	730	1			T20	6		T56	12		T29	3
values[6]	2818	1			T13	1		T16	11		T17	23
values[7]	725	1			T14	4		T15	19		T18	4
values[8]	905	1			T12	2		T41	46		T140	1
values[9]	164	1			T134	7		T227	1		T131	2
minimum	17068	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T230	1		T134	14		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T19	10		T56	11		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	1		T173	17		T229	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T18	9		T49	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T268	1		T269	1		T169	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T140	1		T132	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	1		T134	5		T243	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	15		T15	13		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T132	1		T29	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	13		T107	13		T238	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T20	6		T56	12		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	3		T227	4		T165	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T13	1		T16	11		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T141	1		T222	1		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T14	1		T15	10		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T18	3		T152	1		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T140	1		T29	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T41	25		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T134	5		T131	1		T89	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T227	1		T187	15		T168	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16739	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T57	14		T160	13		T135	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T134	2		T256	13		T234	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T49	1		T236	12		T53	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	13		T165	4		T163	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T18	3		T131	9		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T169	2		T244	11		T176	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T132	12		T153	10		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	2		T243	9		T161	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	15		T15	14		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	11		T29	1		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	13		T107	12		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	1		T157	6		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T227	10		T165	12		T163	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T17	21		T151	14		T270	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T31	1		T64	10		T197	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	3		T15	9		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T18	1		T50	1		T157	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	15		T142	2		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T41	21		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T134	2		T131	1		T89	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T187	15		T168	16		T256	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T57	4		T160	14		T135	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T52	6		T250	5		T131	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T227	1		T168	20		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T197	13		T349	1		T272	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T256	1		T89	7		T267	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T230	1		T134	14		T255	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T19	10		T56	11		T57	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T173	17		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	9		T49	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T268	1		T269	2		T169	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	1		T153	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T134	5		T243	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	13		T132	1		T154	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	1		T237	1		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	28		T152	2		T238	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T20	6		T56	12		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T107	13		T136	3		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T135	11		T225	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T222	1		T31	4		T227	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T13	1		T14	1		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	3		T141	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T29	13		T159	11		T134	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T41	25		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T52	1		T131	1		T247	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T168	16		T271	17		T258	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T197	2		T350	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T256	1		T89	14		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	2		T255	6		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T57	4		T49	1		T160	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	13		T165	4		T163	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	3		T53	24		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T169	2		T253	5		T271	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T153	10		T223	11		T52	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T134	2		T243	9		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	14		T132	12		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	1		T237	12		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	28		T238	12		T235	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T132	11		T29	1		T157	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T107	12		T143	11		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T135	8		T142	14		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T31	1		T227	10		T165	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T14	3		T15	9		T17	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T18	1		T50	1		T157	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	15		T134	2		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T41	21		T156	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T230	1		T134	3		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T19	1		T56	1		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	14		T173	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	6		T49	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T268	1		T269	1		T169	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T140	1		T132	13		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T49	1		T134	3		T243	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	16		T15	15		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	12		T29	2		T237	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	14		T107	13		T238	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T20	1		T56	1		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	1		T227	11		T165	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T13	1		T16	1		T17	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	1		T222	1		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T14	4		T15	10		T30	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T18	3		T152	1		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T140	1		T29	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T12	2		T41	27		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T134	3		T131	2		T89	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T227	1		T187	16		T168	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16860	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T57	5		T160	15		T135	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T134	13		T256	13		T234	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	9		T56	10		T53	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T173	16		T229	13		T139	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T18	6		T30	1		T131	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T169	9		T244	14		T176	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T153	10		T154	9		T156	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T134	4		T243	10		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	14		T15	12		T192	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T136	8		T239	13		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	12		T107	12		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T20	5		T56	11		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	2		T227	3		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T16	10		T254	32		T275	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T31	1		T250	12		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	9		T30	3		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T18	1		T50	2		T273	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T29	11		T52	3		T250	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T41	19		T156	12		T163	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T134	4		T89	4		T302	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T187	14		T168	19		T256	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T255	13		T197	12		T278	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T57	13		T160	12		T135	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T52	4		T250	1		T131	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T227	1		T168	17		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T197	3		T349	1		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T256	2		T89	16		T267	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T230	1		T134	3		T255	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T19	1		T56	1		T57	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	14		T173	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T18	6		T49	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T268	1		T269	2		T169	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	1		T153	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	1		T134	3		T243	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	15		T132	13		T154	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	2		T237	13		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	30		T152	2		T238	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T20	1		T56	1		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T107	13		T136	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T135	9		T225	1		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T222	1		T31	4		T227	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T13	1		T14	4		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T18	3		T141	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T29	17		T159	1		T134	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T12	2		T41	27		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T52	3		T250	4		T247	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T168	19		T290	3		T347	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T197	12		T272	11		T350	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T89	5		T267	10		T351	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	13		T255	13		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T19	9		T56	10		T57	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T173	16		T229	13		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T18	6		T30	1		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T169	9		T253	12		T170	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T153	10		T156	1		T244	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T134	4		T243	10		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	12		T154	9		T192	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T136	8		T239	13		T341	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	26		T226	8		T235	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	5		T56	11		T29	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T107	12		T136	2		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T135	10		T167	4		T239	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T31	1		T227	3		T245	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T15	9		T16	10		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T18	1		T50	2		T250	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	11		T159	10		T134	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T41	19		T156	12		T187	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10