Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22416

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3328

1

T9

14

T12

32

T15

46

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20030

1

T2

20

T3

20

T4

19

auto[1]

5714

1

T9

14

T12

58

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	398	1			T135	16		T223	12		T166	1
values[0]	21	1			T287	10		T329	6		T221	5
values[1]	1064	1			T9	14		T15	27		T222	1
values[2]	605	1			T18	4		T41	46		T29	28
values[3]	500	1			T56	12		T57	18		T134	16
values[4]	2742	1			T13	1		T16	11		T17	23
values[5]	564	1			T12	28		T15	19		T152	1
values[6]	584	1			T140	1		T132	12		T49	2
values[7]	617	1			T12	30		T19	10		T140	1
values[8]	791	1			T20	6		T152	1		T50	7
values[9]	1057	1			T14	4		T49	2		T152	1
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1024	1			T15	27		T29	28		T222	1
values[1]	611	1			T18	4		T41	46		T57	18
values[2]	453	1			T18	12		T56	12		T30	2
values[3]	2786	1			T13	1		T15	19		T16	11
values[4]	682	1			T12	28		T49	2		T152	1
values[5]	457	1			T140	2		T132	12		T137	1
values[6]	648	1			T12	30		T19	10		T56	11
values[7]	815	1			T20	6		T152	1		T50	7
values[8]	937	1			T14	4		T49	2		T152	1
values[9]	311	1			T135	16		T168	14		T242	17
minimum	17020	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T29	13		T225	1		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T15	13		T222	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	3		T41	25		T250	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T57	14		T133	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T18	9		T56	12		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T30	2		T134	14		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T13	1		T16	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	10		T154	10		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	13		T152	1		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T49	1		T30	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	1		T136	3		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T140	1		T132	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T141	1		T132	1		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	15		T19	10		T56	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T20	6		T152	1		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T225	1		T106	1		T192	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	1		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T49	1		T29	2		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T135	8		T97	1		T331	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T168	12		T242	1		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16729	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T9	1		T134	5		T187	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T29	15		T237	12		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	14		T135	8		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	1		T41	21		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T57	4		T51	13		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T18	3		T238	12		T317	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T134	2		T31	1		T255	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T17	21		T151	14		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	9		T154	13		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	13		T134	2		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T49	1		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T236	12		T161	2		T271	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	11		T161	1		T175	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	12		T107	12		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	15		T160	14		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T50	1		T227	10		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T192	9		T167	5		T169	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	3		T153	10		T155	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	1		T223	11		T238	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T135	8		T97	8		T331	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T168	2		T242	16		T267	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T9	13		T134	2		T187	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T135	8		T155	1		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T223	1		T166	1		T249	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T287	10		T329	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T221	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T225	1		T142	1		T156	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T9	1		T15	13		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	3		T41	25		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	1		T230	1		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T56	12		T238	1		T269	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T57	14		T134	14		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T13	1		T16	11		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T154	10		T30	2		T136	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	13		T152	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T15	10		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	1		T136	3		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	1		T132	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T140	1		T141	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	15		T19	10		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T20	6		T152	1		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	13		T225	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T14	1		T49	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T49	1		T29	2		T229	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T135	8		T155	2		T143	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T223	11		T249	2		T168	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T329	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T142	14		T156	12		T242	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	13		T15	14		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T18	1		T41	21		T29	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T51	13		T161	3		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T238	12		T176	3		T198	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T57	4		T134	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T17	21		T18	3		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T154	13		T136	10		T239	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	13		T134	2		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	1		T15	9		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	2		T271	17		T259	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T132	11		T49	1		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	12		T236	12		T158	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	15		T87	16		T299	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	1		T107	12		T157	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T160	14		T192	9		T167	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T14	3		T153	10		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	1		T238	16		T53	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T29	17		T225	1		T237	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T15	15		T222	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T18	3		T41	27		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T57	5		T133	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T18	6		T56	1		T238	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T30	1		T134	3		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T13	1		T16	1		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	10		T154	14		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	14		T152	1		T134	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	2		T49	2		T30	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T140	1		T136	1		T236	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T140	1		T132	12		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T141	1		T132	13		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	16		T19	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T20	1		T152	1		T50	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T225	1		T106	1		T192	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	4		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T49	1		T29	2		T223	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T135	9		T97	9		T331	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T168	3		T242	17		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16870	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T9	14		T134	3		T187	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T29	11		T156	12		T163	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	12		T135	10		T52	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T18	1		T41	19		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T57	13		T51	11		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T18	6		T56	11		T176	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T30	1		T134	13		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T16	10		T159	10		T254	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T15	9		T154	9		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	12		T134	4		T156	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	3		T250	10		T255	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T136	2		T161	2		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T175	1		T274	2		T310	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T107	12		T139	15		T273	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	14		T19	9		T56	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T20	5		T50	2		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T192	16		T167	4		T169	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T153	10		T131	10		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	1		T229	13		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T135	7		T331	9		T297	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T168	11		T267	10		T308	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T288	1		T307	14		T287	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T134	4		T256	9		T347	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T135	9		T155	3		T143	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T223	12		T166	1		T249	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T287	1		T329	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T221	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T225	1		T142	15		T156	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T9	14		T15	15		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	3		T41	27		T29	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	1		T230	1		T51	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	1		T238	13		T269	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T57	5		T134	3		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T13	1		T16	1		T17	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T154	14		T30	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	14		T152	1		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	2		T15	10		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T225	1		T136	1		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T140	1		T132	12		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T140	1		T141	1		T132	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	16		T19	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T20	1		T152	1		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T160	15		T225	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T14	4		T49	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T49	1		T29	2		T229	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T135	7		T147	13		T247	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T249	11		T168	11		T286	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T287	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T221	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T156	12		T163	9		T170	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T15	12		T134	4		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T18	1		T41	19		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T51	11		T161	5		T253	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T56	11		T176	4		T333	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	13		T134	13		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T16	10		T18	6		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T154	9		T30	1		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	12		T134	4		T243	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T15	9		T250	10		T170	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T136	2		T161	2		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T30	3		T255	13		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T273	6		T296	6		T235	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	14		T19	9		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T20	5		T50	2		T107	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T160	12		T192	16		T167	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T153	10		T227	3		T131	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	1		T229	13		T53	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10