Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T12	13		T258	1		T164	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T133	1		T257	1		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	6		T155	1		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	15		T41	25		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	2		T168	1		T241	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T56	11		T152	1		T154	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T30	8		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	13		T49	1		T243	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	10		T152	1		T227	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T153	11		T160	13		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T223	1		T107	13		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T56	12		T142	1		T52	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T159	11		T222	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T140	1		T141	1		T29	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T57	14		T50	6		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T14	1		T18	3		T20	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	1		T140	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T19	10		T132	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	2		T106	1		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T12	13		T260	12		T261	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T258	9		T199	11		T262	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T52	1		T155	2		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	15		T41	21		T242	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T17	21		T18	3		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	1		T168	1		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T154	13		T135	8		T157	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T30	2		T167	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T15	14		T49	1		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	9		T227	10		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T153	10		T160	14		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T223	11		T107	12		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T142	2		T52	2		T53	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T142	14		T156	2		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T29	16		T134	2		T135	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T57	4		T50	1		T236	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	3		T18	1		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	13		T132	12		T51	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T132	11		T134	2		T237	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T238	16		T239	14		T145	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T52	4		T187	15		T163	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	16		T41	27		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T13	1		T16	1		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T225	1		T168	2		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T49	2		T152	1		T154	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	2		T30	7		T167	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	15		T153	11		T243	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	10		T152	1		T227	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T160	15		T134	3		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T159	1		T223	12		T107	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T56	1		T29	17		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	5		T230	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T140	1		T141	1		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T50	5		T236	24		T131	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	4		T18	3		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	14		T140	1		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T132	12		T49	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T30	1		T133	1		T238	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T12	14		T19	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T258	10		T231	17		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16859	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T137	1		T193	1		T253	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T52	3		T163	12		T244	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	14		T41	19		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T16	10		T18	6		T56	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T234	3		T235	14		T47	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T154	9		T135	7		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T30	3		T167	4		T227	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	12		T153	10		T243	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	9		T145	8		T226	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T160	12		T134	4		T156	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T159	10		T107	12		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	11		T29	11		T173	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T57	13		T136	2		T250	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T134	4		T135	10		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T50	2		T46	10		T263	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T18	1		T20	5		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	11		T192	16		T249	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T250	4		T131	10		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	1		T239	13		T145	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T12	12		T19	9		T182	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T252	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T259	7		T89	4		T177	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T253	7		T259	5		T47	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T12	14		T258	1		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T133	1		T257	1		T258	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	4		T155	3		T187	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	16		T41	27		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T29	2		T168	2		T241	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T56	1		T152	1		T154	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	2		T30	7		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	15		T49	2		T243	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	10		T152	1		T227	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T153	11		T160	15		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T223	12		T107	13		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	1		T142	3		T52	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T159	1		T222	1		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T140	1		T141	1		T29	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T57	5		T50	5		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T14	4		T18	3		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	14		T140	1		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T19	1		T132	12		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	1		T106	1		T238	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T12	12		T164	13		T182	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T264	8		T262	14		T265	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	3		T244	9		T247	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	14		T41	19		T253	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T16	10		T18	6		T254	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	1		T241	19		T234	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T56	10		T154	9		T135	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T30	3		T167	4		T255	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	12		T243	10		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T15	9		T227	3		T145	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T153	10		T160	12		T134	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T107	12		T229	13		T189	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T56	11		T53	8		T244	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T159	10		T136	2		T250	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T29	11		T173	16		T134	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T57	13		T50	2		T256	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T18	1		T20	5		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T51	11		T192	16		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T19	9		T134	13		T250	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T30	1		T239	13		T145	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10