Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22561

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3183

1

T12

58

T15

27

T18

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19590

1

T2

20

T3

20

T4

19

auto[1]

6154

1

T9

14

T12

56

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T258	10		T266	1		-	-
values[0]	111	1			T256	2		T89	21		T267	19
values[1]	763	1			T19	10		T56	11		T57	18
values[2]	741	1			T9	14		T18	12		T49	1
values[3]	603	1			T140	1		T137	1		T52	3
values[4]	578	1			T12	30		T15	27		T132	13
values[5]	715	1			T12	26		T152	2		T29	2
values[6]	662	1			T20	6		T56	12		T132	12
values[7]	777	1			T29	3		T222	1		T135	19
values[8]	2808	1			T13	1		T14	4		T15	19
values[9]	1174	1			T12	2		T18	4		T41	46
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1060	1			T19	10		T56	11		T57	18
values[1]	760	1			T9	14		T18	12		T49	1
values[2]	438	1			T140	1		T132	13		T153	21
values[3]	813	1			T12	30		T15	27		T49	1
values[4]	523	1			T12	26		T132	12		T29	2
values[5]	700	1			T20	6		T56	12		T29	3
values[6]	2818	1			T13	1		T16	11		T17	23
values[7]	713	1			T14	4		T15	19		T18	4
values[8]	878	1			T12	2		T41	46		T140	1
values[9]	215	1			T134	7		T225	1		T155	3
minimum	16826	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T230	1		T134	14		T255	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T19	10		T56	11		T57	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	1		T173	17		T229	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	9		T49	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T268	1		T269	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T140	1		T132	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T49	1		T152	2		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	15		T15	13		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T132	1		T29	1		T237	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	13		T107	13		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T20	6		T56	12		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T227	4		T165	2		T163	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1631	1			T13	1		T16	11		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T141	1		T222	1		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	1		T15	10		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	3		T152	1		T50	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T140	1		T29	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T41	25		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T134	5		T155	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T225	1		T227	1		T187	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16672	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T233	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T134	2		T255	6		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T57	4		T49	1		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	13		T165	4		T163	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T18	3		T162	9		T169	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T168	1		T169	2		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T132	12		T153	10		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	2		T243	9		T161	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	15		T15	14		T192	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T132	11		T29	1		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	13		T107	12		T238	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T29	1		T157	6		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T227	10		T165	12		T163	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T17	21		T151	14		T270	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T31	1		T235	8		T64	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	3		T15	9		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T18	1		T50	1		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	15		T142	2		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T41	21		T158	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T134	2		T155	2		T131	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T187	15		T168	16		T271	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T233	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T258	1		T266	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T197	13		T272	12		T252	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T256	1		T89	7		T267	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T230	1		T134	14		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T19	10		T56	11		T57	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	1		T173	17		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T18	9		T49	1		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T268	1		T269	2		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T140	1		T137	1		T52	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	1		T243	11		T250	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	15		T15	13		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T152	2		T29	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	13		T144	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	6		T56	12		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T107	13		T136	3		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T29	2		T135	11		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T222	1		T31	4		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T13	1		T14	1		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T141	1		T50	6		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T29	13		T159	11		T134	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T12	1		T18	3		T41	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T258	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T197	2		T252	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T256	1		T89	14		T267	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T134	2		T255	6		T187	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T57	4		T49	1		T160	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	13		T165	4		T163	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	3		T223	11		T53	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T168	1		T169	2		T253	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T52	2		T192	9		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T243	9		T161	3		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	15		T15	14		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	1		T134	2		T237	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	13		T235	17		T176	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T132	11		T255	2		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T107	12		T238	12		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T29	1		T135	8		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T31	1		T165	12		T64	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T14	3		T15	9		T17	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T50	1		T157	3		T273	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T29	15		T134	2		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	1		T18	1		T41	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T230	1		T134	3		T255	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T19	1		T56	1		T57	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T9	14		T173	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T18	6		T49	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T268	1		T269	1		T168	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T140	1		T132	13		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T49	1		T152	2		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	16		T15	15		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	12		T29	2		T237	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	14		T107	13		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T20	1		T56	1		T29	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T227	11		T165	14		T163	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T13	1		T16	1		T17	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	1		T222	1		T31	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T14	4		T15	10		T30	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	3		T152	1		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T140	1		T29	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	2		T41	27		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T134	3		T155	3		T131	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T225	1		T227	1		T187	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16817	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T134	13		T255	13		T256	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T19	9		T56	10		T57	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T173	16		T229	13		T139	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T18	6		T30	1		T162	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T169	9		T244	14		T176	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T153	10		T154	9		T156	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T134	4		T243	10		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	14		T15	12		T192	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T136	8		T239	13		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	12		T107	12		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T20	5		T56	11		T29	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T227	3		T163	12		T170	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T16	10		T254	32		T275	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T31	1		T250	12		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	9		T30	3		T159	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T18	1		T50	2		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T29	11		T52	3		T250	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	19		T256	9		T163	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T134	4		T194	11		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T187	14		T168	19		T277	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	10		T266	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T197	3		T272	1		T252	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T256	2		T89	16		T267	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T230	1		T134	3		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T19	1		T56	1		T57	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	14		T173	1		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	6		T49	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T268	1		T269	2		T168	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	1		T137	1		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T49	1		T243	10		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	16		T15	15		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T152	2		T29	2		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	14		T144	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T20	1		T56	1		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T107	13		T136	1		T238	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T29	2		T135	9		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T222	1		T31	4		T165	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T13	1		T14	4		T15	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T141	1		T50	5		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T29	17		T159	1		T134	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T12	2		T18	3		T41	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T197	12		T272	11		T252	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T89	5		T267	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T134	13		T255	13		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T19	9		T56	10		T57	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T173	16		T229	13		T139	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T18	6		T30	1		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T169	9		T253	12		T170	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T192	16		T156	1		T244	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T243	10		T250	10		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	14		T15	12		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T134	4		T136	8		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	12		T246	8		T235	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	5		T56	11		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T107	12		T136	2		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T29	1		T135	10		T239	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T31	1		T245	13		T197	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T15	9		T16	10		T30	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T50	2		T250	12		T273	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T29	11		T159	10		T134	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T18	1		T41	19		T156	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10