Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22378

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3366

1

T12

28

T14

4

T15

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19620

1

T2

20

T3

20

T4

19

auto[1]

6124

1

T9

14

T12

26

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	550	1			T18	4		T30	3		T62	1
values[0]	14	1			T213	14		-	-		-	-
values[1]	512	1			T152	1		T29	2		T30	10
values[2]	2838	1			T13	1		T16	11		T17	23
values[3]	725	1			T9	14		T56	11		T57	18
values[4]	706	1			T14	4		T15	19		T41	46
values[5]	779	1			T15	27		T18	12		T152	2
values[6]	885	1			T12	26		T20	6		T49	1
values[7]	648	1			T140	1		T141	1		T132	13
values[8]	735	1			T12	30		T137	1		T223	12
values[9]	965	1			T12	2		T18	4		T19	10
minimum	16387	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	599	1			T140	1		T29	2		T30	10
values[1]	2764	1			T13	1		T16	11		T17	23
values[2]	749	1			T9	14		T57	18		T132	12
values[3]	646	1			T14	4		T15	19		T41	46
values[4]	928	1			T15	27		T18	12		T49	1
values[5]	701	1			T12	26		T20	6		T140	1
values[6]	650	1			T141	1		T132	13		T49	2
values[7]	751	1			T223	12		T237	13		T52	10
values[8]	802	1			T12	32		T18	4		T19	10
values[9]	172	1			T229	14		T147	25		T259	1
minimum	16982	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T30	8		T159	11		T250	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T140	1		T29	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1559	1			T13	1		T16	11		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T56	11		T156	2		T253	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T132	1		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	14		T222	1		T250	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T15	10		T56	12		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	1		T41	25		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	2		T30	2		T51	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T15	13		T18	9		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T230	1		T160	13		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	13		T20	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	1		T29	13		T173	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	1		T132	1		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T52	7		T155	1		T227	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T223	1		T237	1		T238	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	15		T19	10		T29	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T18	3		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T229	14		T147	14		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T278	8		T279	1		T280	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16741	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T107	13		T155	1		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T30	2		T236	10		T247	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	1		T168	1		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T17	21		T151	14		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T156	2		T253	14		T176	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	13		T132	11		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T57	4		T236	12		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	9		T134	2		T158	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	3		T41	21		T165	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T51	13		T142	14		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	14		T18	3		T135	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T160	14		T239	12		T162	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	13		T242	4		T163	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	1		T29	15		T167	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	12		T153	10		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T52	3		T155	2		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T223	11		T237	12		T238	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	15		T29	1		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T18	1		T192	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T147	11		T64	10		T282	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T279	14		T280	2		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T107	12		T155	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	470	1			T18	4		T30	3		T62	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T87	3		T278	8		T280	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T213	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	1		T30	8		T159	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	1		T107	13		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T140	1		T156	2		T241	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	1		T132	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	11		T57	14		T250	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T15	10		T56	12		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	1		T41	25		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T152	2		T30	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T15	13		T18	9		T135	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T230	1		T160	13		T51	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	13		T20	6		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T49	1		T29	13		T173	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	1		T141	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	15		T137	1		T52	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T223	1		T237	1		T238	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T19	10		T29	2		T50	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T12	1		T18	3		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16256	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T169	12		T256	1		T147	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T280	2		T284	1		T285	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T213	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T30	2		T134	4		T161	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T29	1		T107	12		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T17	21		T151	14		T270	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T156	2		T241	15		T169	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	13		T132	11		T154	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T57	4		T236	12		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	9		T134	2		T158	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	3		T41	21		T165	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T142	14		T163	3		T286	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	14		T18	3		T135	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T160	14		T51	13		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	13		T145	8		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	1		T29	15		T167	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T132	12		T153	10		T169	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	15		T52	3		T155	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T223	11		T237	12		T238	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	1		T50	1		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T18	1		T192	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	7		T159	1		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	1		T29	2		T168	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T13	1		T16	1		T17	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T56	1		T156	3		T253	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	14		T132	12		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T57	5		T222	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	10		T56	1		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	4		T41	27		T165	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T152	2		T30	1		T51	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	15		T18	6		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T230	1		T160	15		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	14		T20	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	2		T29	17		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T141	1		T132	13		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T52	7		T155	3		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T223	12		T237	13		T238	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	16		T19	1		T29	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	2		T18	3		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T229	1		T147	12		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T278	1		T279	15		T280	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16850	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T107	13		T155	3		T281	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	3		T159	10		T250	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T241	19		T169	9		T267	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T16	10		T154	9		T254	32
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T56	10		T156	1		T253	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T161	2		T286	4		T274	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T57	13		T250	10		T187	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	9		T56	11		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T41	19		T162	8		T234	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T30	1		T51	11		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T15	12		T18	6		T135	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T160	12		T239	11		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	12		T20	5		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T29	11		T173	16		T167	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T153	10		T239	13		T259	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T52	3		T227	3		T255	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T156	12		T239	3		T175	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	14		T19	9		T29	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T18	1		T192	16		T139	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T229	13		T147	13		T64	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T278	7		T272	20		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T134	17		T161	5		T273	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T107	12		T287	9		T251	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T18	4		T30	3		T62	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T87	3		T278	1		T280	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T213	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T152	1		T30	7		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T29	2		T107	13		T155	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T140	1		T156	3		T241	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	14		T132	12		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T56	1		T57	5		T250	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	10		T56	1		T134	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	4		T41	27		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T152	2		T30	1		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T15	15		T18	6		T135	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T230	1		T160	15		T51	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	14		T20	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	2		T29	17		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T140	1		T141	1		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	16		T137	1		T52	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T223	12		T237	13		T238	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T19	1		T29	2		T50	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	2		T18	3		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16387	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T169	10		T147	13		T64	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T278	7		T284	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T213	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T30	3		T159	10		T134	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T107	12		T235	14		T288	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T16	10		T254	32		T275	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T156	1		T241	19		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	9		T161	2		T168	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T56	10		T57	13		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	9		T56	11		T134	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	19		T234	3		T263	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T30	1		T163	6		T289	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	12		T18	6		T135	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T160	12		T51	11		T31	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	12		T20	5		T145	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T29	11		T173	16		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T153	10		T244	14		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	14		T52	3		T227	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T239	16		T175	1		T290	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	9		T29	1		T50	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T18	1		T192	16		T139	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10