Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22128

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T9

14

T12

58

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19946

1

T2

20

T3

20

T4

19

auto[1]

5798

1

T12

26

T13

1

T14

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T57	18		T139	16		T156	4
values[0]	27	1			T134	7		T291	1		T292	19
values[1]	800	1			T15	19		T20	6		T56	11
values[2]	657	1			T159	11		T134	7		T243	20
values[3]	875	1			T12	30		T15	27		T152	1
values[4]	847	1			T12	2		T140	1		T141	1
values[5]	2849	1			T12	26		T13	1		T16	11
values[6]	592	1			T140	1		T56	12		T237	13
values[7]	532	1			T19	10		T49	2		T29	31
values[8]	432	1			T18	16		T132	13		T137	1
values[9]	1066	1			T9	14		T14	4		T41	46
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T15	19		T20	6		T56	11
values[1]	712	1			T15	27		T243	20		T268	1
values[2]	889	1			T12	30		T152	2		T159	11
values[3]	2997	1			T12	28		T13	1		T16	11
values[4]	763	1			T140	1		T49	1		T50	7
values[5]	482	1			T56	12		T237	13		T167	10
values[6]	506	1			T18	4		T19	10		T132	13
values[7]	525	1			T9	14		T18	12		T41	46
values[8]	834	1			T14	4		T57	18		T49	1
values[9]	279	1			T153	21		T107	25		T139	16
minimum	17059	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T29	1		T52	6		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	10		T20	6		T56	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	13		T243	11		T250	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T268	1		T161	7		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T152	2		T238	1		T250	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	15		T159	11		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T13	1		T16	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	14		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T140	1		T49	1		T192	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	6		T158	1		T169	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T56	12		T237	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T167	5		T161	4		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T18	3		T19	10		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	1		T29	15		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T225	1		T157	1		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	1		T18	9		T41	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T57	14		T49	1		T154	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T14	1		T30	8		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T294	1		T45	5		T295	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T153	11		T107	13		T139	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16739	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T134	5		T236	1		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T29	1		T52	1		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	9		T132	11		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T15	14		T243	9		T53	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T161	6		T89	14		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T238	12		T131	9		T161	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	15		T223	11		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T17	21		T151	14		T270	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	14		T160	14		T249	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T192	9		T165	4		T187	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T50	1		T158	10		T169	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T237	12		T145	1		T296	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T167	5		T161	2		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T18	1		T132	12		T157	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	1		T29	16		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T157	3		T253	5		T259	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	13		T18	3		T41	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T57	4		T154	13		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	3		T30	2		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T297	18		T261	4		T298	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	10		T107	12		T47	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T134	2		T236	10		T274	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T57	14		T156	2		T227	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T139	16		T269	1		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T134	5		T291	1		T292	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	1		T227	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T15	10		T20	6		T56	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T243	11		T52	6		T250	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T159	11		T134	5		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	13		T152	1		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	15		T223	1		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T152	1		T52	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T140	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T13	1		T16	11		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	13		T50	6		T229	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	1		T56	12		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T158	1		T161	4		T175	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T19	10		T157	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T49	1		T29	15		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T18	3		T132	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T18	9		T142	1		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T49	1		T154	10		T173	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T9	1		T14	1		T41	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T57	4		T156	2		T227	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T256	13		T299	11		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T134	2		T292	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T29	1		T273	8		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T15	9		T132	11		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T243	9		T52	1		T53	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T134	2		T161	3		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	14		T238	12		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	15		T223	11		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T52	2		T31	1		T239	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T160	14		T236	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T17	21		T151	14		T270	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	13		T50	1		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T237	12		T165	4		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T158	10		T161	2		T175	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T157	6		T168	1		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	1		T29	16		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T18	1		T132	12		T253	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T18	3		T142	14		T242	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T154	13		T135	8		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	13		T14	3		T41	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	2		T52	4		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T15	10		T20	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T15	15		T243	10		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T268	1		T161	8		T293	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T152	2		T238	13		T250	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	16		T159	1		T223	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T13	1		T16	1		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	16		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T140	1		T49	1		T192	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	5		T158	11		T169	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	1		T237	13		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T167	6		T161	4		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T18	3		T19	1		T132	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T49	2		T29	19		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T225	1		T157	4		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	14		T18	6		T41	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T57	5		T49	1		T154	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	4		T30	7		T142	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T294	1		T45	3		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T153	11		T107	13		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16863	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T134	3		T236	11		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T52	3		T226	8		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T15	9		T20	5		T56	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T15	12		T243	10		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	5		T170	12		T245	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T250	10		T131	10		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	14		T159	10		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T16	10		T254	32		T275	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	12		T160	12		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T192	16		T170	4		T235	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	2		T169	10		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T56	11		T296	6		T248	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T167	4		T161	2		T244	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T18	1		T19	9		T288	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	12		T30	1		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T253	7		T259	7		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T18	6		T41	19		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T57	13		T154	9		T173	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T30	3		T256	13		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T45	2		T295	7		T297	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T153	10		T107	12		T139	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T273	6		T169	9		T244	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T134	4		T264	8		T213	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T57	5		T156	3		T227	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T139	1		T269	1		T256	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	3		T291	1		T292	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	2		T227	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	10		T20	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T243	10		T52	4		T250	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T159	1		T134	3		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T15	15		T152	1		T238	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T12	16		T223	12		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T152	1		T52	3		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	2		T140	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T13	1		T16	1		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	14		T50	5		T229	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	1		T56	1		T237	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T158	11		T161	4		T175	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T19	1		T157	7		T168	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	2		T29	19		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T18	3		T132	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T18	6		T142	15		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T49	1		T154	14		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T9	14		T14	4		T41	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T57	13		T156	1		T227	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T139	15		T256	13		T170	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T134	4		T292	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T273	6		T169	9		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	9		T20	5		T56	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T243	10		T52	3		T250	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T159	10		T134	4		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	12		T250	10		T131	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	14		T136	2		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	1		T239	13		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T160	12		T249	11		T239	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T16	10		T254	32		T275	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	12		T50	2		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T56	11		T296	6		T248	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T161	2		T175	1		T253	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T19	9		T288	14		T197	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	12		T30	1		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T18	1		T253	7		T259	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T18	6		T290	3		T164	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T154	9		T173	16		T135	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T41	19		T153	10		T30	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10