Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19967

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3001

1

T11

2

T13

4

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16965

1

T2

20

T3

20

T4

1

auto[1]

6003

1

T10

8

T13

4

T17

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	80	1			T298	22		T310	38		T311	7
values[0]	37	1			T312	10		T202	15		T313	1
values[1]	655	1			T13	4		T137	1		T121	21
values[2]	740	1			T19	9		T42	7		T120	18
values[3]	610	1			T39	35		T173	3		T44	3
values[4]	604	1			T19	5		T137	1		T78	17
values[5]	3046	1			T16	1		T18	5		T20	28
values[6]	667	1			T10	3		T155	21		T168	1
values[7]	679	1			T10	5		T129	13		T118	24
values[8]	694	1			T11	2		T120	17		T43	11
values[9]	1140	1			T14	2		T15	8		T17	1
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1000	1			T13	4		T42	7		T137	1
values[1]	578	1			T19	9		T39	35		T120	18
values[2]	612	1			T173	3		T44	3		T80	11
values[3]	3042	1			T18	5		T19	5		T20	28
values[4]	659	1			T16	1		T46	20		T155	10
values[5]	544	1			T10	3		T155	11		T45	11
values[6]	726	1			T10	5		T43	11		T129	13
values[7]	646	1			T11	2		T120	17		T168	1
values[8]	829	1			T14	2		T15	8		T17	1
values[9]	275	1			T125	16		T262	11		T201	26
minimum	14057	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T121	1		T82	1		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	3		T42	6		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	9		T140	5		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	11		T120	10		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T173	1		T44	2		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T80	11		T236	15		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1770	1			T18	1		T19	5		T20	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T137	1		T141	16		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T16	1		T155	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	15		T168	1		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	2		T155	1		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	1		T122	1		T255	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	3		T43	9		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T80	14		T142	14		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T168	1		T82	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T120	9		T169	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T14	1		T15	6		T19	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	1		T186	6		T123	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T262	1		T264	14		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T125	9		T201	14		T284	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13920	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T121	12		T82	2		T124	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	1		T42	1		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T242	2		T145	8		T213	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T39	24		T120	8		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T173	2		T44	1		T123	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T236	12		T247	1		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T18	4		T165	21		T78	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T143	15		T271	9		T176	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T155	9		T121	11		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T46	5		T251	12		T171	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	1		T155	10		T45	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T138	1		T122	11		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	2		T43	2		T118	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T252	20		T126	15		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T82	15		T139	12		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	1		T120	8		T281	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	1		T15	2		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T123	11		T156	2		T232	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T262	10		T264	12		T315	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T125	7		T201	12		T284	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	3		T25	2		T13	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T298	11		T311	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T310	22		T316	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T312	10		T202	8		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T121	1		T142	15		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	3		T137	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T19	9		T140	5		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	6		T120	10		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T173	1		T44	2		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T39	11		T236	15		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	5		T78	10		T80	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T137	1		T80	11		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T16	1		T18	1		T20	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	15		T140	12		T141	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	2		T155	2		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T168	1		T81	1		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	3		T129	13		T118	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T80	14		T122	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T43	9		T82	10		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T120	9		T169	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T14	1		T15	6		T19	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T17	1		T186	6		T123	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T298	11		T311	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T310	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T202	7		T317	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T121	12		T242	2		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T121	7		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T82	2		T124	1		T145	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T42	1		T120	8		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T173	2		T44	1		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T39	24		T236	12		T143	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T78	7		T124	14		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T247	1		T171	5		T271	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T18	4		T165	21		T304	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T46	5		T251	12		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	1		T155	19		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T138	1		T128	13		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	2		T118	9		T82	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T122	11		T252	20		T127	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	2		T82	15		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	1		T120	8		T126	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	1		T15	2		T139	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T123	11		T125	7		T156	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T121	13		T82	3		T124	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T13	4		T42	6		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T19	1		T140	1		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T39	25		T120	9		T244	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T173	3		T44	2		T123	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T80	1		T236	13		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T18	5		T19	1		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T137	1		T141	1		T143	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T16	1		T155	10		T121	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	6		T168	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	3		T155	11		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T138	2		T122	12		T255	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	4		T43	8		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T80	1		T142	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T168	1		T82	16		T139	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	2		T120	9		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T14	2		T15	6		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	1		T186	1		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T262	11		T264	13		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T125	8		T201	13		T284	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14037	1			T2	20		T3	20		T4	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T142	14		T283	12		T156	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T42	1		T138	5		T153	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T19	8		T140	4		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	10		T120	9		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	1		T123	12		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T80	10		T236	14		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T19	4		T20	25		T164	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T141	15		T263	12		T266	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T151	18		T169	11		T171	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	14		T140	11		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	3		T138	6		T240	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T169	12		T147	11		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T10	1		T43	3		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T80	13		T142	13		T252	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T82	9		T197	21		T242	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	8		T169	8		T281	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T15	2		T19	14		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T186	5		T123	9		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T264	13		T298	10		T318	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T125	8		T201	13		T284	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T305	9		T282	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T298	12		T311	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T310	17		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T312	1		T202	8		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T121	13		T142	1		T242	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	4		T137	1		T121	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T19	1		T140	1		T82	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T42	6		T120	9		T244	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T173	3		T44	2		T123	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	25		T236	13		T143	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	1		T78	8		T80	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T137	1		T80	1		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T16	1		T18	5		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	6		T140	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	3		T155	21		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T168	1		T81	1		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	4		T129	1		T118	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T80	1		T122	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T43	8		T82	16		T243	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	2		T120	9		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T14	2		T15	6		T19	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T186	1		T123	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	10		T311	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T310	21		T316	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T312	9		T202	7		T317	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	14		T242	2		T156	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T138	5		T153	10		T207	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	8		T140	4		T145	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T42	1		T120	9		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	1		T123	12		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	10		T236	14		T272	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	4		T78	9		T80	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T80	10		T247	1		T171	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T20	25		T164	15		T167	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	14		T140	11		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	3		T138	6		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T169	12		T267	9		T319	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T129	12		T118	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T80	13		T142	13		T252	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T43	3		T82	9		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	8		T169	8		T126	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T15	2		T19	14		T141	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T186	5		T123	9		T125	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26