Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22462

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3282

1

T12

28

T15

19

T20

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19995

1

T2

20

T3

20

T4

19

auto[1]

5749

1

T9

14

T12

28

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T20	6		T49	1		-	-
values[0]	35	1			T239	28		T301	1		T302	6
values[1]	595	1			T140	1		T225	2		T52	7
values[2]	687	1			T49	1		T29	3		T134	16
values[3]	604	1			T19	10		T57	18		T29	2
values[4]	708	1			T12	30		T18	12		T152	1
values[5]	786	1			T56	11		T152	2		T153	21
values[6]	868	1			T12	26		T18	4		T41	46
values[7]	854	1			T9	14		T15	27		T132	25
values[8]	739	1			T12	2		T14	4		T15	19
values[9]	3060	1			T13	1		T16	11		T17	23
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T140	1		T225	2		T192	26
values[1]	639	1			T49	1		T29	3		T134	16
values[2]	730	1			T19	10		T57	18		T29	2
values[3]	610	1			T12	30		T18	12		T152	1
values[4]	890	1			T12	26		T18	4		T41	46
values[5]	921	1			T15	27		T140	1		T132	25
values[6]	2796	1			T9	14		T13	1		T14	4
values[7]	767	1			T12	2		T15	19		T134	7
values[8]	684	1			T20	6		T56	12		T154	23
values[9]	112	1			T49	1		T142	1		T189	5
minimum	16821	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T140	1		T225	1		T192	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T225	1		T157	1		T131	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	1		T29	2		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	1		T135	11		T136	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T19	10		T57	14		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	1		T173	17		T250	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	15		T18	9		T159	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T152	1		T193	1		T293	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T18	3		T56	11		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	13		T41	25		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	13		T140	1		T132	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T29	13		T30	2		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T9	1		T13	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T243	11		T51	16		T229	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	5		T157	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T15	10		T139	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T154	10		T53	16		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T20	6		T56	12		T107	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T49	1		T142	1		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T189	4		T264	3		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T52	6		T296	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T192	9		T238	16		T168	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T157	3		T131	9		T239	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	1		T134	2		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T135	8		T136	10		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T57	4		T236	12		T256	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	1		T156	12		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	15		T18	3		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T87	16		T259	16		T258	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T18	1		T153	10		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	13		T41	21		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	14		T132	23		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T29	15		T135	8		T155	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T9	13		T14	3		T17	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T243	9		T51	13		T244	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	2		T157	6		T165	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T15	9		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T154	13		T53	24		T187	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T107	12		T237	12		T131	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T304	3		T305	11		T306	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T189	1		T307	1		T308	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T52	1		T296	6		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T49	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T20	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T301	1		T302	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T239	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T140	1		T225	1		T192	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T225	1		T52	6		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T29	2		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T136	9		T156	15		T227	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T19	10		T57	14		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T29	1		T173	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	15		T18	9		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	1		T250	11		T163	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T56	11		T152	2		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T30	8		T255	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T18	3		T140	1		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	13		T41	25		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	1		T15	13		T132	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	13		T137	1		T135	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T134	5		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T15	10		T243	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T13	1		T16	11		T17	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T56	12		T107	13		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T302	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T239	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T192	9		T238	16		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	1		T157	3		T145	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	1		T134	2		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T136	10		T156	14		T227	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T57	4		T142	14		T236	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	1		T135	8		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	15		T18	3		T155	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T163	5		T259	16		T258	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	10		T50	1		T168	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	2		T255	6		T87	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T18	1		T49	1		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	13		T41	21		T160	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	13		T15	14		T132	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	15		T135	8		T51	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	3		T134	2		T145	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	1		T15	9		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T17	21		T151	14		T154	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T107	12		T237	12		T131	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T140	1		T225	1		T192	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T225	1		T157	4		T131	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	1		T29	2		T134	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T137	1		T135	9		T136	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	1		T57	5		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	2		T173	1		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	16		T18	6		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T152	1		T193	1		T293	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	3		T56	1		T152	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	14		T41	27		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T15	15		T140	1		T132	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T29	17		T30	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T9	14		T13	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T243	10		T51	18		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T134	3		T157	7		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	2		T15	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T154	14		T53	32		T187	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T20	1		T56	1		T107	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T49	1		T142	1		T303	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T189	4		T264	1		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T52	4		T296	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T192	16		T162	8		T175	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T131	10		T239	13		T163	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	1		T134	13		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T135	10		T136	8		T156	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T19	9		T57	13		T250	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T173	16		T250	10		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	14		T18	6		T159	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T87	15		T259	16		T64	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T18	1		T56	10		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	12		T41	19		T30	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	12		T134	4		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	11		T30	1		T135	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T16	10		T254	32		T275	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T243	10		T51	11		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T134	4		T309	12		T265	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	9		T139	15		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T154	9		T53	8		T273	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T20	5		T56	11		T107	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T304	1		T305	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T189	1		T264	2		T310	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T52	3		T296	6		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T49	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T20	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T301	1		T302	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T239	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T140	1		T225	1		T192	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T225	1		T52	4		T157	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	1		T29	2		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T136	11		T156	16		T227	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	1		T57	5		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	2		T173	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	16		T18	6		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	1		T250	1		T163	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T56	1		T152	2		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	7		T255	7		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T18	3		T140	1		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	14		T41	27		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T9	14		T15	15		T132	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T29	17		T137	1		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	4		T134	3		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	2		T15	10		T243	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T13	1		T16	1		T17	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T56	1		T107	13		T237	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T20	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T302	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T239	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T192	16		T162	8		T175	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T52	3		T163	6		T234	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	1		T134	13		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T136	8		T156	13		T227	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	9		T57	13		T239	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T173	16		T135	10		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	14		T18	6		T249	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T250	10		T163	3		T259	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T56	10		T153	10		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	3		T255	13		T87	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T18	1		T134	4		T250	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	12		T41	19		T30	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	12		T145	2		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	11		T135	7		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T134	4		T145	8		T248	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	9		T243	10		T139	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T16	10		T154	9		T254	32
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T56	11		T107	12		T189	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10