Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20029

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

2939

1

T13

4

T15

8

T16

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17213

1

T2

20

T3

20

T4

1

auto[1]

5755

1

T11

2

T15

8

T18

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	307	1			T19	5		T186	6		T140	5
values[0]	5	1			T268	5		-	-		-	-
values[1]	627	1			T14	2		T16	1		T155	21
values[2]	777	1			T17	1		T46	20		T43	11
values[3]	859	1			T39	35		T168	1		T243	10
values[4]	504	1			T10	3		T42	7		T173	3
values[5]	3143	1			T11	2		T13	4		T18	5
values[6]	548	1			T120	18		T137	1		T82	5
values[7]	645	1			T15	8		T82	3		T139	13
values[8]	734	1			T120	17		T168	1		T121	12
values[9]	803	1			T10	5		T19	15		T168	1
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T14	2		T16	1		T43	11
values[1]	790	1			T17	1		T46	20		T140	12
values[2]	761	1			T39	35		T42	7		T173	3
values[3]	2966	1			T10	3		T18	5		T20	28
values[4]	688	1			T11	2		T13	4		T19	9
values[5]	583	1			T120	18		T137	1		T82	8
values[6]	691	1			T15	8		T129	13		T29	1
values[7]	615	1			T120	17		T168	2		T121	12
values[8]	867	1			T10	5		T19	20		T186	6
values[9]	157	1			T124	2		T272	1		T156	6
minimum	14174	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	1		T155	1		T197	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T16	1		T43	9		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T46	15		T140	12		T82	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	1		T152	1		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T168	1		T243	1		T151	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	11		T42	6		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1691	1			T10	2		T18	1		T20	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T121	1		T132	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	1		T123	23		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	3		T19	9		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	10		T137	1		T82	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T139	1		T236	15		T156	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T129	13		T240	4		T145	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	6		T29	1		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T168	1		T121	1		T141	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T120	9		T168	1		T80	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T10	3		T186	6		T140	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	20		T121	1		T118	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T124	1		T272	1		T156	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T269	11		T277	3		T328	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13911	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T151	19		T126	12		T207	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T155	10		T242	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T43	2		T155	9		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T46	5		T82	15		T124	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T152	6		T86	1		T176	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T243	9		T176	11		T329	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	24		T42	1		T173	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T10	1		T18	4		T165	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T121	7		T257	2		T171	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	1		T123	19		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	1		T247	1		T281	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T120	8		T82	6		T138	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T139	12		T236	12		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T240	3		T145	8		T174	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	2		T247	1		T143	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T121	11		T125	7		T171	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T120	8		T125	5		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	2		T45	3		T151	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T121	12		T118	9		T78	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T124	1		T276	14		T216	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T277	8		T328	12		T330	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T151	15		T126	13		T268	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T186	6		T140	5		T45	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T19	5		T178	17		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T268	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	1		T155	1		T197	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	1		T155	1		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T46	15		T140	12		T82	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	1		T43	9		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T168	1		T243	1		T151	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	11		T142	14		T238	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	2		T183	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T42	6		T173	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1804	1			T11	1		T18	1		T20	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	3		T19	9		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T120	10		T137	1		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T281	16		T156	9		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T82	1		T145	7		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	6		T139	1		T236	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T168	1		T121	1		T129	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T120	9		T29	1		T125	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	3		T80	11		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T19	15		T168	1		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T45	3		T124	15		T126	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T306	6		T277	8		T328	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T268	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T14	1		T155	10		T242	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T155	9		T138	5		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T46	5		T82	15		T124	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T43	2		T152	6		T86	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T243	9		T267	2		T176	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	24		T238	10		T128	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T10	1		T44	1		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T42	1		T173	2		T143	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1123	1			T11	1		T18	4		T165	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T13	1		T121	7		T247	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T120	8		T82	4		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T281	13		T156	2		T284	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T82	2		T145	8		T174	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	2		T139	12		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T121	11		T240	3		T125	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	8		T125	5		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	2		T151	10		T246	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T121	12		T118	9		T78	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	2		T155	11		T197	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T16	1		T43	8		T155	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T46	6		T140	1		T82	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T17	1		T152	7		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T168	1		T243	10		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	25		T42	6		T173	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T10	3		T18	5		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T121	8		T132	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T11	2		T123	21		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	4		T19	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T120	9		T137	1		T82	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	13		T236	13		T156	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	1		T240	4		T145	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T15	6		T29	1		T247	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T168	1		T121	12		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T120	9		T168	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	4		T186	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T19	2		T121	13		T118	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T124	2		T272	1		T156	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T269	1		T277	9		T328	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14031	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T151	16		T126	14		T207	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T197	9		T242	2		T252	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T43	3		T138	5		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T46	14		T140	11		T82	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	7		T147	11		T187	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T151	4		T169	11		T329	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	10		T42	1		T142	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T20	25		T164	15		T167	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T171	4		T201	11		T207	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T123	21		T242	8		T283	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T19	8		T281	15		T284	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T120	9		T138	6		T267	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T236	14		T156	8		T284	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T129	12		T240	3		T145	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	2		T247	1		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T141	2		T125	8		T171	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T120	8		T80	13		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T186	5		T140	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	18		T118	14		T78	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T156	5		T216	6		T286	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T269	10		T277	2		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T266	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T151	18		T126	11		T207	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T186	1		T140	1		T45	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T19	1		T178	1		T306	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T268	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	2		T155	11		T197	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T16	1		T155	10		T138	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T46	6		T140	1		T82	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T17	1		T43	8		T152	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T168	1		T243	10		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	25		T142	1		T238	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	3		T183	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	6		T173	3		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T11	2		T18	5		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	4		T19	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T120	9		T137	1		T82	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T281	14		T156	3		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T82	3		T145	9		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T15	6		T139	13		T236	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T168	1		T121	12		T129	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T120	9		T29	1		T125	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	4		T80	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	1		T168	1		T121	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T186	5		T140	4		T45	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T19	4		T178	16		T277	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T268	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T197	9		T242	2		T171	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T138	5		T151	18		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	14		T140	11		T82	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	3		T169	12		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T151	4		T169	11		T267	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	10		T142	13		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T44	1		T251	14		T250	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	1		T171	4		T201	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T20	25		T164	15		T167	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T19	8		T207	11		T284	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T120	9		T138	6		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T281	15		T156	8		T284	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T145	6		T174	12		T263	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	2		T236	14		T247	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T129	12		T141	2		T240	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T120	8		T125	3		T145	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	1		T80	10		T141	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T19	14		T118	14		T78	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26