Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19974

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

5770

1

T12

30

T13

1

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19968

1

T2

20

T3

20

T4

19

auto[1]

5776

1

T12

2

T13

1

T15

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T131	2		T311	2		T312	2
values[0]	138	1			T140	1		T248	21		T313	11
values[1]	595	1			T49	1		T153	21		T29	3
values[2]	669	1			T19	10		T20	6		T56	12
values[3]	640	1			T49	2		T50	7		T159	11
values[4]	683	1			T9	14		T141	1		T132	13
values[5]	676	1			T18	12		T140	1		T29	28
values[6]	670	1			T15	19		T18	4		T152	2
values[7]	631	1			T14	4		T29	2		T134	16
values[8]	844	1			T12	2		T15	27		T41	46
values[9]	3391	1			T12	56		T13	1		T16	11
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T19	10		T140	1		T57	18
values[1]	2731	1			T13	1		T16	11		T17	23
values[2]	660	1			T141	1		T49	2		T50	7
values[3]	756	1			T132	13		T173	17		T225	1
values[4]	646	1			T9	14		T18	12		T140	1
values[5]	728	1			T152	2		T135	16		T167	10
values[6]	695	1			T14	4		T15	19		T18	4
values[7]	806	1			T12	28		T15	27		T41	46
values[8]	687	1			T12	30		T56	11		T154	23
values[9]	300	1			T243	20		T161	9		T165	13
minimum	16827	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T49	1		T153	11		T30	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	10		T140	1		T57	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T20	6		T56	12		T51	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1529	1			T13	1		T16	11		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T50	6		T30	2		T159	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T141	1		T49	1		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T132	1		T173	17		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T31	4		T166	1		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	1		T18	9		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T107	13		T236	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T152	1		T167	5		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T152	1		T135	8		T255	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	10		T18	3		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T223	1		T229	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	14		T132	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	13		T41	25		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T56	11		T154	10		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	15		T160	13		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T161	6		T193	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T243	11		T165	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T314	1		T200	11		T315	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T153	10		T30	2		T157	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T57	4		T29	1		T255	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	13		T187	14		T169	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	893	1			T17	21		T151	14		T270	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	1		T136	10		T242	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T49	1		T134	2		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T132	12		T238	16		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	1		T156	12		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	13		T18	3		T29	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T107	12		T236	12		T146	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T167	5		T165	4		T145	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T135	8		T255	2		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	9		T18	1		T29	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	3		T223	11		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	14		T132	11		T192	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T15	14		T41	21		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T154	13		T156	2		T131	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	15		T160	14		T142	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T161	3		T89	14		T316	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T243	9		T165	12		T256	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T200	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T131	1		T312	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T311	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T313	9		T305	13		T211	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T140	1		T248	10		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	1		T153	11		T30	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	2		T137	1		T249	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T20	6		T56	12		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T19	10		T57	14		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	6		T159	11		T173	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T49	1		T134	5		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T132	1		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T141	1		T230	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T18	9		T140	1		T29	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T107	13		T236	1		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	10		T18	3		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T152	1		T255	9		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	1		T134	14		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T135	8		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T12	1		T56	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	13		T41	25		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	13		T154	10		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1812	1			T12	15		T13	1		T16	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T131	1		T312	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T313	2		T305	10		T211	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T248	11		T181	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T153	10		T30	2		T157	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T29	1		T249	2		T87	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	13		T143	7		T187	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T57	4		T134	2		T237	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	1		T136	10		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T49	1		T134	2		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	13		T132	12		T238	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T31	1		T131	9		T317	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T18	3		T29	15		T239	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T107	12		T236	12		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T15	9		T18	1		T167	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T255	2		T161	2		T187	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	1		T134	2		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	3		T135	8		T223	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T132	11		T192	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	14		T41	21		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	13		T154	13		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1121	1			T12	15		T17	21		T151	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T49	1		T153	11		T30	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T19	1		T140	1		T57	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	1		T56	1		T51	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1205	1			T13	1		T16	1		T17	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T50	5		T30	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T141	1		T49	2		T230	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T132	13		T173	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T31	4		T166	1		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	14		T18	6		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T107	13		T236	13		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T152	1		T167	6		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T152	1		T135	9		T255	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	10		T18	3		T29	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	4		T223	12		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	16		T132	12		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T15	15		T41	27		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	1		T154	14		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T12	16		T160	15		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T161	4		T193	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T243	10		T165	13		T256	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T314	1		T200	14		T315	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T153	10		T30	3		T239	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	9		T57	13		T29	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T20	5		T56	11		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1217	1			T16	10		T254	32		T134	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T50	2		T30	1		T159	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	4		T131	10		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T173	16		T250	12		T239	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	1		T156	12		T145	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T18	6		T29	11		T250	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T107	12		T147	13		T253	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T167	4		T47	14		T318	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T135	7		T255	8		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T15	9		T18	1		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T229	13		T52	3		T136	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	12		T192	16		T162	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	12		T41	19		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T56	10		T154	9		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	14		T160	12		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T161	5		T89	5		T288	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T243	10		T32	1		T267	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T200	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T131	2		T312	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T311	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T313	3		T305	11		T211	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T140	1		T248	12		T315	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	1		T153	11		T30	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T29	2		T137	1		T249	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T20	1		T56	1		T51	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	1		T57	5		T134	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T50	5		T159	1		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	2		T134	3		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	14		T132	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T141	1		T230	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T18	6		T140	1		T29	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T107	13		T236	13		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	10		T18	3		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T152	1		T255	3		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T29	2		T134	3		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	4		T135	9		T223	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	2		T56	1		T132	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T15	15		T41	27		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	14		T154	14		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1486	1			T12	16		T13	1		T16	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T313	8		T305	12		T211	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T248	9		T181	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T153	10		T30	3		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T29	1		T249	11		T87	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T20	5		T56	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	9		T57	13		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	2		T159	10		T173	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T134	4		T168	11		T170	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	1		T250	12		T239	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	1		T131	10		T289	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	6		T29	11		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T107	12		T156	12		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	9		T18	1		T250	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T255	8		T161	2		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T134	13		T245	22		T47	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T135	7		T52	3		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T56	10		T192	16		T241	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T15	12		T41	19		T135	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	12		T154	9		T156	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1447	1			T12	14		T16	10		T160	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10