Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19581

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3387

1

T10

3

T14

2

T15

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16920

1

T2

20

T3

20

T4

1

auto[1]

6048

1

T10

5

T11

2

T14

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	382	1			T137	1		T118	24		T124	30
values[0]	18	1			T331	18		-	-		-	-
values[1]	544	1			T10	5		T14	2		T19	5
values[2]	588	1			T155	10		T132	1		T82	5
values[3]	870	1			T120	18		T186	6		T168	1
values[4]	523	1			T19	15		T168	1		T44	3
values[5]	507	1			T173	3		T168	1		T80	14
values[6]	702	1			T10	3		T13	4		T15	8
values[7]	752	1			T16	1		T46	20		T43	11
values[8]	721	1			T183	1		T82	3		T151	26
values[9]	3345	1			T11	2		T17	1		T18	5
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	604	1			T10	5		T19	5		T120	17
values[1]	614	1			T155	10		T243	10		T151	5
values[2]	800	1			T19	15		T120	18		T186	6
values[3]	517	1			T168	1		T121	13		T129	13
values[4]	508	1			T10	3		T15	8		T173	3
values[5]	746	1			T16	1		T43	11		T137	1
values[6]	3135	1			T13	4		T18	5		T20	28
values[7]	786	1			T39	35		T183	1		T82	3
values[8]	972	1			T11	2		T17	1		T19	9
values[9]	94	1			T138	2		T237	1		T241	1
minimum	14192	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	3		T19	5		T138	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T120	9		T132	1		T80	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T155	1		T151	5		T142	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T243	1		T143	1		T146	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T19	15		T44	2		T123	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T120	10		T186	6		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T168	1		T121	1		T129	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T81	1		T262	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T258	1		T271	1		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	2		T15	6		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	1		T43	9		T236	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T137	1		T80	11		T242	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1760	1			T13	3		T18	1		T20	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T82	10		T151	16		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T82	1		T247	2		T252	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	11		T183	1		T255	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T42	6		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T17	1		T19	9		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T237	1		T241	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T138	1		T282	12		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13935	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T14	1		T121	1		T251	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	2		T138	8		T125	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T120	8		T82	4		T240	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T155	9		T143	15		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T243	9		T143	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	1		T123	11		T124	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T120	8		T121	11		T213	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T121	12		T78	7		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T262	10		T246	1		T267	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T271	9		T175	6		T86	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	1		T15	2		T173	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T43	2		T236	12		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T242	2		T252	10		T145	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T13	1		T18	4		T46	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T82	15		T151	10		T238	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T82	2		T247	1		T252	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	24		T152	6		T153	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T42	1		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T247	1		T128	13		T201	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T176	15		T329	9		T254	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T138	1		T282	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T14	1		T121	7		T251	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T118	15		T124	15		T237	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	1		T174	16		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T331	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	3		T19	5		T141	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T120	9		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T155	1		T138	7		T151	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T132	1		T82	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T123	10		T124	1		T142	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T120	10		T186	6		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T19	15		T168	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T121	1		T213	1		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T123	13		T258	1		T271	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T173	1		T168	1		T80	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	3		T152	1		T197	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	2		T15	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	1		T46	15		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T82	10		T238	1		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T82	1		T142	14		T242	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T183	1		T151	16		T255	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T11	1		T18	1		T20	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T17	1		T19	9		T39	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T118	9		T124	15		T268	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T174	11		T36	14		T282	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T331	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	2		T125	5		T171	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	1		T120	8		T121	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T155	9		T138	8		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T82	4		T243	9		T127	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T123	11		T124	1		T125	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	8		T281	13		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T44	1		T121	12		T78	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T121	11		T213	1		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T123	8		T271	9		T86	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T173	2		T138	4		T139	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T175	6		T267	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	1		T15	2		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	5		T43	2		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T82	15		T238	10		T242	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T82	2		T242	2		T252	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T151	10		T153	10		T126	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T11	1		T18	4		T42	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T39	24		T138	1		T152	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	4		T19	1		T138	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T120	9		T132	1		T80	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T155	10		T151	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T243	10		T143	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T19	1		T44	2		T123	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T120	9		T186	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T168	1		T121	13		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T81	1		T262	11		T246	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T258	1		T271	10		T175	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	3		T15	6		T173	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T43	8		T236	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	1		T80	1		T242	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T13	4		T18	5		T20	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T82	16		T151	11		T238	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T82	3		T247	2		T252	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T39	25		T183	1		T255	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	2		T42	6		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T17	1		T19	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T237	1		T241	1		T176	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T138	2		T282	14		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14057	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T14	2		T121	8		T251	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T19	4		T138	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	8		T80	7		T240	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T151	4		T142	14		T156	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T146	14		T127	8		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T19	14		T44	1		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T120	9		T186	5		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	12		T78	9		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T332	1		T267	4		T296	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T159	6		T264	1		T333	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	2		T80	13		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	3		T236	14		T197	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T80	10		T242	2		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T20	25		T46	14		T164	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T82	9		T151	15		T300	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T247	1		T252	18		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	10		T153	10		T126	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T42	1		T118	14		T45	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T19	8		T141	15		T201	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T329	10		T254	2		T334	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T282	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T171	3		T267	7		T335	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T251	14		T331	8		T310	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T118	10		T124	17		T237	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T137	1		T174	12		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T331	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	4		T19	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	2		T120	9		T121	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T155	10		T138	9		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T132	1		T82	5		T243	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T123	12		T124	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T120	9		T186	1		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	1		T168	1		T44	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T121	12		T213	2		T262	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	9		T258	1		T271	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T173	3		T168	1		T80	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T152	1		T197	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	3		T15	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	1		T46	6		T43	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T82	16		T238	11		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T82	3		T142	1		T242	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T183	1		T151	11		T255	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T11	2		T18	5		T20	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T17	1		T19	1		T39	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T118	14		T124	13		T268	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T174	15		T36	14		T282	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T331	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	1		T19	4		T141	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T120	8		T80	7		T240	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	6		T151	4		T272	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	14		T127	8		T283	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T123	9		T142	14		T125	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T120	9		T186	5		T140	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	14		T44	1		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T174	12		T267	4		T306	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T123	12		T159	6		T264	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T80	13		T138	5		T197	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T197	21		T267	9		T216	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	2		T80	10		T252	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T46	14		T43	3		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T82	9		T242	2		T300	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	13		T242	6		T252	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T151	15		T153	10		T126	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T20	25		T42	1		T164	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	8		T39	10		T141	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26