Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22136

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3608

1

T9

14

T12

58

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19913

1

T2

20

T3

20

T4

19

auto[1]

5831

1

T12

26

T13

1

T14

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T269	1		T319	4		-	-
values[0]	125	1			T168	36		T291	1		T259	12
values[1]	695	1			T15	19		T20	6		T56	11
values[2]	659	1			T159	11		T134	7		T243	20
values[3]	881	1			T12	30		T15	27		T223	12
values[4]	880	1			T12	2		T141	1		T152	2
values[5]	2776	1			T12	26		T13	1		T16	11
values[6]	654	1			T140	1		T49	1		T135	19
values[7]	523	1			T19	10		T49	2		T29	31
values[8]	454	1			T18	16		T132	13		T137	1
values[9]	1291	1			T9	14		T14	4		T41	46
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T15	19		T20	6		T56	11
values[1]	699	1			T15	27		T134	7		T243	20
values[2]	952	1			T12	30		T152	2		T159	11
values[3]	2942	1			T12	26		T13	1		T16	11
values[4]	768	1			T12	2		T140	1		T49	1
values[5]	473	1			T56	12		T237	13		T250	5
values[6]	506	1			T18	4		T19	10		T132	13
values[7]	532	1			T9	14		T18	12		T41	46
values[8]	746	1			T14	4		T57	18		T49	1
values[9]	364	1			T153	21		T30	10		T137	1
minimum	16848	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T29	1		T52	6		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T15	10		T20	6		T56	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T15	13		T243	11		T250	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T134	5		T268	1		T161	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T152	2		T31	4		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	15		T159	11		T223	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T13	1		T16	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	13		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T140	1		T49	1		T192	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T50	6		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T56	12		T237	1		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T250	5		T167	5		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T18	3		T19	10		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T49	1		T29	15		T30	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T225	1		T155	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T18	9		T41	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T57	14		T49	1		T154	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	1		T142	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T294	1		T163	7		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	11		T30	8		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T168	20		T194	1		T320	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T29	1		T52	1		T255	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	9		T132	11		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T15	14		T243	9		T53	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T134	2		T161	6		T241	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T31	1		T238	12		T131	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	15		T223	11		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T17	21		T151	14		T270	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	13		T160	14		T249	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T192	9		T165	4		T187	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	1		T50	1		T158	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T237	12		T145	1		T296	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T167	5		T161	2		T253	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T18	1		T132	12		T157	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	1		T29	16		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T155	2		T157	3		T253	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	13		T18	3		T41	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T57	4		T154	13		T135	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	3		T142	2		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T163	3		T297	18		T321	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T153	10		T30	2		T107	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T168	16		T194	1		T320	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T319	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T259	7		T322	1		T323	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T168	20		T291	1		T308	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	1		T227	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	10		T20	6		T56	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T243	11		T52	6		T53	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T159	11		T134	5		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T15	13		T238	1		T250	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	15		T223	1		T136	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T152	2		T52	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	1		T141	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T13	1		T16	11		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	13		T140	1		T50	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T140	1		T49	1		T237	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T135	11		T158	1		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T19	10		T157	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T49	1		T29	15		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T18	3		T132	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	9		T142	1		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T57	14		T49	1		T154	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T9	1		T14	1		T41	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T319	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T259	5		T323	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T168	16		T308	15		T292	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T29	1		T273	8		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	9		T132	11		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T243	9		T52	1		T53	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T134	2		T161	3		T89	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T15	14		T238	12		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	15		T223	11		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T52	2		T31	1		T238	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T160	14		T236	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T17	21		T151	14		T270	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T12	13		T50	1		T169	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T237	12		T165	4		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T135	8		T158	10		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T157	6		T168	1		T242	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T49	1		T29	16		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T18	1		T132	12		T157	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T18	3		T142	14		T242	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T57	4		T154	13		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T9	13		T14	3		T41	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T29	2		T52	4		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T15	10		T20	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T15	15		T243	10		T250	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T134	3		T268	1		T161	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T152	2		T31	4		T238	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T12	16		T159	1		T223	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T13	1		T16	1		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	14		T140	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T140	1		T49	1		T192	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	2		T50	5		T158	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T56	1		T237	13		T145	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T250	1		T167	6		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T18	3		T19	1		T132	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T49	2		T29	19		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T225	1		T155	3		T157	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	14		T18	6		T41	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T57	5		T49	1		T154	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	4		T142	3		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T294	1		T163	4		T45	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T153	11		T30	7		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T168	17		T194	2		T320	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	3		T255	13		T273	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T15	9		T20	5		T56	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	12		T243	10		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T134	4		T161	5		T241	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T31	1		T250	10		T131	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	14		T159	10		T136	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T16	10		T254	32		T275	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	12		T160	12		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T192	16		T175	1		T170	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T50	2		T169	10		T299	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T56	11		T296	6		T248	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T250	4		T167	4		T161	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T18	1		T19	9		T288	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	12		T30	1		T134	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T253	7		T259	7		T246	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T18	6		T41	19		T51	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T57	13		T154	9		T173	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T256	13		T289	6		T87	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T163	6		T45	2		T295	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T153	10		T30	3		T107	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T168	19		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T319	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T259	7		T322	1		T323	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T168	17		T291	1		T308	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	2		T227	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	10		T20	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T243	10		T52	4		T53	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T159	1		T134	3		T268	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T15	15		T238	13		T250	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	16		T223	12		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T152	2		T52	3		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T12	2		T141	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T13	1		T16	1		T17	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	14		T140	1		T50	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	1		T49	1		T237	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	9		T158	11		T161	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T19	1		T157	7		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T49	2		T29	19		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T18	3		T132	13		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T18	6		T142	15		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T57	5		T49	1		T154	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T9	14		T14	4		T41	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T319	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	5		T323	6		T324	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T168	19		T308	12		T292	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T273	6		T169	9		T226	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T15	9		T20	5		T56	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T243	10		T52	3		T53	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T159	10		T134	4		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	12		T250	22		T131	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	14		T136	2		T161	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T239	13		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T160	12		T249	11		T239	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T16	10		T56	11		T254	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	12		T50	2		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T175	1		T296	6		T248	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T135	10		T161	2		T244	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T19	9		T246	14		T288	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	12		T30	1		T134	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T18	1		T253	7		T247	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T18	6		T247	13		T290	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T57	13		T154	9		T173	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T41	19		T153	10		T30	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10