Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22968

1

T2

20

T3

20

T4

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19986

1

T2

20

T3

20

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

2982

1

T11

2

T13

4

T17

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16965

1

T2

20

T3

20

T4

1

auto[1]

6003

1

T10

8

T13

4

T17

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19141

1

T2

20

T3

20

T4

1

auto[1]

3827

1

T10

6

T11

1

T25

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	367	1			T15	8		T17	1		T125	16
values[0]	36	1			T312	10		T202	15		T317	11
values[1]	716	1			T13	4		T137	1		T121	21
values[2]	686	1			T19	9		T42	7		T120	18
values[3]	591	1			T39	35		T173	3		T44	3
values[4]	606	1			T19	5		T168	1		T137	1
values[5]	3109	1			T16	1		T18	5		T20	28
values[6]	630	1			T10	3		T155	21		T121	12
values[7]	620	1			T10	5		T129	13		T118	24
values[8]	708	1			T11	2		T120	17		T43	11
values[9]	883	1			T14	2		T19	15		T186	6
minimum	14016	1			T2	20		T3	20		T4	1

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T13	4		T42	7		T140	5
values[1]	584	1			T19	9		T39	35		T120	18
values[2]	657	1			T173	3		T44	3		T80	11
values[3]	3000	1			T18	5		T19	5		T20	28
values[4]	658	1			T16	1		T46	20		T155	10
values[5]	547	1			T10	3		T155	11		T45	11
values[6]	710	1			T10	5		T129	13		T118	24
values[7]	648	1			T11	2		T120	17		T43	11
values[8]	878	1			T14	2		T17	1		T186	6
values[9]	246	1			T15	8		T19	15		T125	16
minimum	14206	1			T2	20		T3	20		T4	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

4222

1

T10

1

T15

2

T19

26

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T140	5		T82	1		T124	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	3		T42	6		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T19	9		T242	3		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	11		T120	10		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T173	1		T44	2		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T80	11		T236	15		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1727	1			T18	1		T19	5		T20	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T137	1		T141	16		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	1		T155	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	15		T168	1		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	2		T155	1		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T138	1		T122	1		T169	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	3		T129	13		T118	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T80	14		T142	14		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	9		T168	1		T82	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T120	9		T169	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T14	1		T243	1		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T186	6		T123	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T15	6		T19	15		T262	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T125	9		T201	14		T336	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13954	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T137	1		T138	6		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T82	2		T124	1		T145	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T42	1		T121	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T242	2		T213	1		T248	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	24		T120	8		T244	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T173	2		T44	1		T123	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T236	12		T247	1		T143	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T18	4		T165	21		T78	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T143	15		T171	5		T271	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T155	9		T121	11		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T46	5		T251	12		T171	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	1		T155	10		T45	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T138	1		T122	11		T128	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	2		T118	9		T82	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T252	20		T126	15		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T43	2		T82	15		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	1		T120	8		T281	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	1		T243	9		T139	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T123	11		T156	2		T232	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T15	2		T262	10		T264	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T125	7		T201	12		T336	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	3		T25	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	4		T308	9		T337	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T15	6		T257	1		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	1		T125	9		T201	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T312	10		T202	8		T317	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T121	1		T142	15		T156	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	3		T137	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T19	9		T140	5		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T42	6		T120	10		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T173	1		T44	2		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	11		T236	15		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T19	5		T168	1		T78	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T137	1		T80	11		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1745	1			T16	1		T18	1		T20	28
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	15		T168	1		T140	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	2		T155	2		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T81	1		T138	1		T255	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	3		T129	13		T118	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T80	14		T122	1		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T43	9		T82	10		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T120	9		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T14	1		T19	15		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T186	6		T123	10		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13898	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T15	2		T257	2		T264	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T125	7		T201	12		T216	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T202	7		T317	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T121	12		T32	1		T305	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T121	7		T138	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T82	2		T124	1		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	1		T120	8		T244	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T173	2		T44	1		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	24		T236	12		T143	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T78	7		T124	14		T125	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T247	1		T171	5		T271	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T18	4		T165	21		T304	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T46	5		T251	12		T171	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	1		T155	19		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T138	1		T128	13		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	2		T118	9		T82	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	11		T252	20		T127	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T43	2		T82	15		T243	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	1		T120	8		T126	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	1		T139	12		T239	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T123	11		T156	2		T232	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	3		T25	2		T13	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T140	1		T82	3		T124	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	4		T42	6		T121	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T19	1		T242	3		T213	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T39	25		T120	9		T244	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T173	3		T44	2		T123	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T80	1		T236	13		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T18	5		T19	1		T20	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T137	1		T141	1		T143	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	1		T155	10		T121	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	6		T168	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	3		T155	11		T45	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T138	2		T122	12		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	4		T129	1		T118	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T80	1		T142	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	8		T168	1		T82	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	2		T120	9		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T14	2		T243	10		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	1		T186	1		T123	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T15	6		T19	1		T262	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T125	8		T201	13		T336	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14075	1			T2	20		T3	20		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T137	1		T138	5		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T140	4		T142	14		T145	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T42	1		T153	10		T213	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T19	8		T242	2		T248	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	10		T120	9		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T44	1		T123	12		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T80	10		T236	14		T247	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T19	4		T20	25		T164	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T141	15		T171	4		T263	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	18		T169	11		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	14		T140	11		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	3		T138	6		T240	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T169	12		T147	11		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T129	12		T118	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T80	13		T142	13		T252	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	3		T82	9		T197	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	8		T169	8		T281	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T141	2		T248	2		T292	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T186	5		T123	9		T156	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T15	2		T19	14		T264	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T125	8		T201	13		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T156	5		T305	9		T312	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T138	5		T265	9		T308	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T15	6		T257	3		T258	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T17	1		T125	8		T201	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T312	1		T202	8		T317	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T121	13		T142	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	4		T137	1		T121	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T19	1		T140	1		T82	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T42	6		T120	9		T244	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T173	3		T44	2		T123	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	25		T236	13		T143	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T19	1		T168	1		T78	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T137	1		T80	1		T247	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T16	1		T18	5		T20	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	6		T168	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	3		T155	21		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T81	1		T138	2		T255	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	4		T129	1		T118	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T80	1		T122	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T43	8		T82	16		T243	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	2		T120	9		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T14	2		T19	1		T168	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T186	1		T123	12		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14016	1			T2	20		T3	20		T4	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T15	2		T264	13		T178	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T125	8		T201	13		T216	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T312	9		T202	7		T317	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T142	14		T156	5		T305	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T138	5		T153	10		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T19	8		T140	4		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T42	1		T120	9		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	1		T123	12		T151	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	10		T236	14		T272	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T19	4		T78	9		T80	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T80	10		T247	1		T171	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T20	25		T164	15		T167	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T46	14		T140	11		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T45	3		T138	6		T240	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T169	12		T267	9		T299	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	1		T129	12		T118	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T80	13		T142	13		T252	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	3		T82	9		T197	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T120	8		T169	8		T126	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T19	14		T141	2		T197	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T186	5		T123	9		T156	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

18746

1

T2

20

T3

20

T4

1

auto[1]

auto[0]

4222

1

T10

1

T15

2

T19

26