Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25744

1

T2

20

T3

20

T4

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22440

1

T2

20

T3

20

T4

19

auto[ADC_CTRL_FILTER_COND_OUT]

3304

1

T9

14

T12

32

T15

46

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19971

1

T2

20

T3

20

T4

19

auto[1]

5773

1

T9

14

T12

58

T13

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21816

1

T2

20

T3

20

T4

19

auto[1]

3928

1

T9

13

T12

29

T14

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T143	8		T247	5		T325	26
values[0]	92	1			T15	27		T52	7		T287	10
values[1]	936	1			T9	14		T222	1		T134	7
values[2]	689	1			T18	4		T41	46		T29	28
values[3]	494	1			T56	12		T57	18		T134	16
values[4]	2702	1			T12	2		T13	1		T16	11
values[5]	577	1			T12	26		T15	19		T152	1
values[6]	622	1			T140	1		T132	12		T49	2
values[7]	648	1			T12	30		T19	10		T140	1
values[8]	763	1			T20	6		T152	1		T160	27
values[9]	1368	1			T14	4		T49	2		T152	1
minimum	16801	1			T2	20		T3	20		T4	19

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1221	1			T9	14		T15	27		T29	28
values[1]	594	1			T18	4		T41	46		T57	18
values[2]	508	1			T18	12		T56	12		T134	16
values[3]	2761	1			T13	1		T15	19		T16	11
values[4]	646	1			T12	28		T49	2		T152	1
values[5]	542	1			T12	30		T140	2		T132	12
values[6]	611	1			T19	10		T56	11		T141	1
values[7]	810	1			T20	6		T152	1		T50	7
values[8]	878	1			T14	4		T152	1		T153	21
values[9]	357	1			T49	2		T135	16		T242	17
minimum	16816	1			T2	20		T3	20		T4	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

4085

1

T12

26

T15

21

T16

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T29	13		T237	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T9	1		T15	13		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T18	3		T41	25		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T57	14		T133	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	9		T56	12		T238	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T134	14		T31	4		T255	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T13	1		T16	11		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T15	10		T154	10		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	13		T152	1		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T49	1		T30	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T140	1		T225	1		T136	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	15		T140	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T141	1		T132	1		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	10		T56	11		T173	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T20	6		T152	1		T50	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T160	13		T225	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	1		T152	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T29	2		T223	1		T229	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T49	1		T135	8		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T49	1		T242	1		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T187	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T29	15		T237	12		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T9	13		T15	14		T134	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T18	1		T41	21		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T57	4		T51	13		T161	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	3		T238	12		T317	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T134	2		T31	1		T255	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T17	21		T151	14		T29	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	9		T154	13		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	13		T134	2		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T49	1		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T236	12		T161	2		T271	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	15		T132	11		T161	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T132	12		T107	12		T158	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T165	4		T162	9		T87	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T50	1		T227	10		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T160	14		T192	9		T167	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	3		T153	10		T155	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	1		T223	11		T238	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T135	8		T97	8		T290	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T242	16		T310	15		T327	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T187	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T143	1		T247	4		T325	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T287	10		T328	15		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T15	13		T52	6		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T225	1		T142	1		T190	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T222	1		T134	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T18	3		T41	25		T29	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T133	1		T230	1		T51	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T56	12		T238	1		T269	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T57	14		T134	14		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T13	1		T16	11		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T154	10		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	13		T152	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T15	10		T268	1		T250	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T225	1		T136	3		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T140	1		T132	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T140	1		T141	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	15		T19	10		T56	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T20	6		T152	1		T107	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T160	13		T225	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	442	1			T14	1		T49	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T49	1		T29	2		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16670	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T143	7		T247	1		T325	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T320	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T328	10		T329	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T15	14		T52	1		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T142	14		T242	4		T163	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	13		T134	2		T135	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T18	1		T41	21		T29	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T51	13		T161	3		T147	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T238	12		T198	12		T330	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T57	4		T134	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T17	21		T18	3		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T154	13		T136	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	13		T134	2		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	9		T145	1		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T161	2		T271	17		T259	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	11		T49	1		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T132	12		T50	1		T236	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	15		T271	7		T87	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T107	12		T157	3		T158	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T160	14		T192	9		T167	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T14	3		T153	10		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T29	1		T223	11		T238	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	2		T29	4		T30	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T29	17		T237	13		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T9	14		T15	15		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	3		T41	27		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T57	5		T133	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T18	6		T56	1		T238	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T134	3		T31	4		T255	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T13	1		T16	1		T17	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T15	10		T154	14		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	14		T152	1		T134	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	2		T49	2		T30	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T140	1		T225	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	16		T140	1		T132	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T141	1		T132	13		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T19	1		T56	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T20	1		T152	1		T50	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T160	15		T225	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T14	4		T152	1		T153	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T29	2		T223	12		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T49	1		T135	9		T97	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T49	1		T242	17		T326	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T187	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T29	11		T156	12		T163	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	12		T134	4		T135	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	1		T41	19		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T57	13		T51	11		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T18	6		T56	11		T176	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T134	13		T31	1		T255	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T16	10		T159	10		T254	32
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	9		T154	9		T30	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	12		T134	4		T156	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T30	3		T250	10		T255	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T136	2		T161	2		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	14		T175	1		T274	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T107	12		T139	15		T273	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	9		T56	10		T173	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T20	5		T50	2		T227	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T160	12		T192	16		T167	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T153	10		T131	10		T189	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	1		T229	13		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T135	7		T290	3		T331	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T310	2		T308	12		T332	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T143	8		T247	2		T325	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T320	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T287	1		T328	11		T329	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T15	15		T52	4		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T225	1		T142	15		T190	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	14		T222	1		T134	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T18	3		T41	27		T29	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T133	1		T230	1		T51	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T56	1		T238	13		T269	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T57	5		T134	3		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T13	1		T16	1		T17	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	2		T154	14		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	14		T152	1		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	10		T268	1		T250	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T225	1		T136	1		T161	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T140	1		T132	12		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T140	1		T141	1		T132	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	16		T19	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T20	1		T152	1		T107	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T160	15		T225	1		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	424	1			T14	4		T49	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T49	1		T29	2		T223	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16801	1			T2	20		T3	20		T4	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T247	3		T325	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T287	9		T328	14		T272	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T15	12		T52	3		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T163	9		T170	17		T245	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T134	4		T135	10		T250	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	1		T41	19		T29	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	11		T161	5		T253	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T56	11		T245	20		T333	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T57	13		T134	13		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T16	10		T18	6		T159	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T154	9		T30	1		T136	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	12		T134	4		T243	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T15	9		T250	10		T170	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T136	2		T161	2		T226	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T30	3		T255	13		T187	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T50	2		T273	6		T296	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	14		T19	9		T56	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T20	5		T107	12		T139	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T160	12		T192	16		T167	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T153	10		T135	7		T227	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	1		T229	13		T249	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21659

1

T2

20

T3

20

T4

19

auto[1]

auto[0]

4085

1

T12

26

T15

21

T16

10