AES/MASKED Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	87.526us	1	1	100.00
V1	smoke	aes_smoke	7.000s	179.526us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	65.806us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	53.966us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	965.181us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	526.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	78.071us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	53.966us	20	20	100.00
		aes_csr_aliasing	5.000s	526.457us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	179.526us	50	50	100.00
		aes_config_error	15.000s	452.661us	50	50	100.00
		aes_stress	3.083m	2.051ms	50	50	100.00
V2	key_length	aes_smoke	7.000s	179.526us	50	50	100.00
		aes_config_error	15.000s	452.661us	50	50	100.00
		aes_stress	3.083m	2.051ms	50	50	100.00
V2	back2back	aes_stress	3.083m	2.051ms	50	50	100.00
		aes_b2b	43.000s	725.095us	50	50	100.00
V2	backpressure	aes_stress	3.083m	2.051ms	50	50	100.00
V2	multi_message	aes_smoke	7.000s	179.526us	50	50	100.00
		aes_config_error	15.000s	452.661us	50	50	100.00
		aes_stress	3.083m	2.051ms	50	50	100.00
		aes_alert_reset	1.667m	3.320ms	50	50	100.00
V2	failure_test	aes_config_error	15.000s	452.661us	50	50	100.00
		aes_alert_reset	1.667m	3.320ms	50	50	100.00
		aes_man_cfg_err	7.000s	169.208us	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	408.275us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	1.402ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.667m	3.320ms	50	50	100.00
V2	stress	aes_stress	3.083m	2.051ms	50	50	100.00
V2	sideload	aes_stress	3.083m	2.051ms	50	50	100.00
		aes_sideload	20.000s	638.653us	50	50	100.00
V2	deinitialization	aes_deinit	20.000s	1.586ms	50	50	100.00
V2	alert_test	aes_alert_test	5.000s	53.943us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	117.547us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	117.547us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	65.806us	5	5	100.00
		aes_csr_rw	3.000s	53.966us	20	20	100.00
		aes_csr_aliasing	5.000s	526.457us	5	5	100.00
		aes_same_csr_outstanding	4.000s	67.573us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	65.806us	5	5	100.00
		aes_csr_rw	3.000s	53.966us	20	20	100.00
		aes_csr_aliasing	5.000s	526.457us	5	5	100.00
		aes_same_csr_outstanding	4.000s	67.573us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	2.833m	4.007ms	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	148.852us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	1.370ms	5	5	100.00
		aes_tl_intg_err	5.000s	472.995us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	472.995us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.667m	3.320ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	179.526us	50	50	100.00
		aes_stress	3.083m	2.051ms	50	50	100.00
		aes_alert_reset	1.667m	3.320ms	50	50	100.00
		aes_core_fi	46.000s	10.080ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	181.515us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.083m	2.051ms	50	50	100.00
		aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.083m	2.051ms	50	50	100.00
		aes_sideload	20.000s	638.653us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	408.959us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.083m	2.051ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.083m	2.051ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	187.488us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	187.488us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.006ms	342	350	97.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	187.488us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.667m	3.320ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_ctr_fi	5.000s	113.786us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	187.488us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	279	300	93.00
		aes_cipher_fi	45.000s	10.006ms	342	350	97.71
V2S		TOTAL			955	985	96.95
V3		TOTAL			0	0	--
		TOTAL			1552	1582	98.10

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	8	72.73

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.47	99.02	97.58	99.41	95.87	95.66	97.78	98.67	92.09

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test aes_cipher_fi has 3 failures.
  - 23.aes_cipher_fi.1182701498
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:24dfb7d7-cdfd-4553-8ae2-512d876b7730
```
  - 84.aes_cipher_fi.4283959076
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/84.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8fc05a39-d96b-4b5c-9143-cc03715740ba
```
  - ... and 1 more failures.
- Test aes_control_fi has 14 failures.
  - 31.aes_control_fi.217164871
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job ID: smart:4c3f04d3-cc37-4d5b-a594-554ea5689341
```
  - 51.aes_control_fi.2483929466
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:40244cb7-5002-4426-87b5-99c7d3bc848f
```
  - ... and 12 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_control_fi has 7 failures.

7.aes_control_fi.3024972473
Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006801197 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006801197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.aes_control_fi.2852717617
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log

  UVM_FATAL @ 10006715272 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006715272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:

Test aes_cipher_fi has 5 failures.

41.aes_cipher_fi.439227136
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10010209771 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010209771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

104.aes_cipher_fi.2975679274
Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/104.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10007841221 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007841221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 29.aes_core_fi.1801688810
    Line 278, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10080222280 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10080222280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```