AES/MASKED Simulation Results

Sunday October 01 2023 19:02:47 UTC

GitHub Revision: `7b89440c3`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3649974514

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	59.958us	1	1	100.00
V1	smoke	aes_smoke	28.000s	840.037us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	132.202us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	101.565us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	3.153ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	665.900us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	53.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	101.565us	20	20	100.00
		aes_csr_aliasing	4.000s	665.900us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	28.000s	840.037us	50	50	100.00
		aes_config_error	10.000s	222.556us	50	50	100.00
		aes_stress	1.700m	6.208ms	50	50	100.00
V2	key_length	aes_smoke	28.000s	840.037us	50	50	100.00
		aes_config_error	10.000s	222.556us	50	50	100.00
		aes_stress	1.700m	6.208ms	50	50	100.00
V2	back2back	aes_stress	1.700m	6.208ms	50	50	100.00
		aes_b2b	44.000s	1.039ms	50	50	100.00
V2	backpressure	aes_stress	1.700m	6.208ms	50	50	100.00
V2	multi_message	aes_smoke	28.000s	840.037us	50	50	100.00
		aes_config_error	10.000s	222.556us	50	50	100.00
		aes_stress	1.700m	6.208ms	50	50	100.00
		aes_alert_reset	10.000s	155.324us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	71.230us	50	50	100.00
		aes_config_error	10.000s	222.556us	50	50	100.00
		aes_alert_reset	10.000s	155.324us	50	50	100.00
V2	trigger_clear_test	aes_clear	23.000s	1.167ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	613.627us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	155.324us	50	50	100.00
V2	stress	aes_stress	1.700m	6.208ms	50	50	100.00
V2	sideload	aes_stress	1.700m	6.208ms	50	50	100.00
		aes_sideload	11.000s	3.180ms	50	50	100.00
V2	deinitialization	aes_deinit	28.000s	1.226ms	50	50	100.00
V2	stress_all	aes_stress_all	5.383m	11.871ms	9	10	90.00
V2	alert_test	aes_alert_test	4.000s	75.866us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	221.430us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	221.430us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	132.202us	5	5	100.00
		aes_csr_rw	3.000s	101.565us	20	20	100.00
		aes_csr_aliasing	4.000s	665.900us	5	5	100.00
		aes_same_csr_outstanding	4.000s	252.892us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	132.202us	5	5	100.00
		aes_csr_rw	3.000s	101.565us	20	20	100.00
		aes_csr_aliasing	4.000s	665.900us	5	5	100.00
		aes_same_csr_outstanding	4.000s	252.892us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	25.000s	1.628ms	49	50	98.00
V2S	fault_inject	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	256.179us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	969.087us	5	5	100.00
		aes_tl_intg_err	6.000s	500.051us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	500.051us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	155.324us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	28.000s	840.037us	50	50	100.00
		aes_stress	1.700m	6.208ms	50	50	100.00
		aes_alert_reset	10.000s	155.324us	50	50	100.00
		aes_core_fi	46.000s	10.004ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	62.110us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	105.828us	50	50	100.00
		aes_stress	1.700m	6.208ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.700m	6.208ms	50	50	100.00
		aes_sideload	11.000s	3.180ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	105.828us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	105.828us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	105.828us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	105.828us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	105.828us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.700m	6.208ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.700m	6.208ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	793.980us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	793.980us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	10.005ms	334	350	95.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	793.980us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	155.324us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_ctr_fi	9.000s	165.991us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	793.980us	50	50	100.00
		aes_control_fi	54.000s	10.030ms	287	300	95.67
		aes_cipher_fi	49.000s	10.005ms	334	350	95.43
V2S		TOTAL			953	985	96.75
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.867m	11.966ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1559	1602	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	99.03	97.56	99.42	95.86	95.66	97.78	99.12	98.38

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_control_fi has 9 failures.
  - 10.aes_control_fi.3408283788
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:b93fecc7-771e-40b0-af7a-d28d629b6c0a
```
  - 23.aes_control_fi.3770906149
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:fff90281-d6c1-4c57-96e9-86d5fe49fa76
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 5 failures.
  - 17.aes_cipher_fi.1778889287
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ab9f44ce-bd0b-4e80-b291-c7757fa968d1
```
  - 86.aes_cipher_fi.2114161490
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e4fe21d5-b053-4e2a-b2c8-1bed96be7740
```
  - ... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_cipher_fi has 10 failures.

18.aes_cipher_fi.3886947744
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10018107324 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018107324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

82.aes_cipher_fi.2185864190
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/82.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10011002444 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011002444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.1829033107
Line 1521, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10799166097 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10799166097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.1800394959
Line 1320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16964645912 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 16964645912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.3128075433
Line 1029, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1002732730 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1002732730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.1871910925
Line 839, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11965707418 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 11965707418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:

Test aes_control_fi has 4 failures.

95.aes_control_fi.3656872224
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/95.aes_control_fi/latest/run.log

  UVM_FATAL @ 10019613104 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019613104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

134.aes_control_fi.4133393054
Line 288, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/134.aes_control_fi/latest/run.log

  UVM_FATAL @ 10017440588 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017440588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

44.aes_core_fi.3947107265
Line 273, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_core_fi/latest/run.log

  UVM_FATAL @ 10023185855 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023185855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.aes_core_fi.4214257106
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/52.aes_core_fi/latest/run.log

  UVM_FATAL @ 10004078299 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004078299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

5.aes_stress_all.3234791864
Line 25525, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 430781444 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 430722620 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 430781444 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 430722620 PS)
  UVM_ERROR @ 430781444 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 29.aes_reseed.3332568858
    Line 350, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/29.aes_reseed/latest/run.log
```
  UVM_FATAL @  61666798 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  61666798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

Test aes_cipher_fi has 1 failures.

242.aes_cipher_fi.749346582
Line 276, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/242.aes_cipher_fi/latest/run.log

  UVM_ERROR @  51659514 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  51659514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---