AES/MASKED Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	115.876us	1	1	100.00
V1	smoke	aes_smoke	30.000s	764.650us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	73.247us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	57.262us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	4.249ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	76.182us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	58.588us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	57.262us	20	20	100.00
		aes_csr_aliasing	4.000s	76.182us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	30.000s	764.650us	50	50	100.00
		aes_config_error	13.000s	415.883us	50	50	100.00
		aes_stress	37.000s	2.104ms	50	50	100.00
V2	key_length	aes_smoke	30.000s	764.650us	50	50	100.00
		aes_config_error	13.000s	415.883us	50	50	100.00
		aes_stress	37.000s	2.104ms	50	50	100.00
V2	back2back	aes_stress	37.000s	2.104ms	50	50	100.00
		aes_b2b	1.583m	1.216ms	50	50	100.00
V2	backpressure	aes_stress	37.000s	2.104ms	50	50	100.00
V2	multi_message	aes_smoke	30.000s	764.650us	50	50	100.00
		aes_config_error	13.000s	415.883us	50	50	100.00
		aes_stress	37.000s	2.104ms	50	50	100.00
		aes_alert_reset	15.000s	561.573us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	411.552us	50	50	100.00
		aes_config_error	13.000s	415.883us	50	50	100.00
		aes_alert_reset	15.000s	561.573us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	364.105us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	306.647us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	561.573us	50	50	100.00
V2	stress	aes_stress	37.000s	2.104ms	50	50	100.00
V2	sideload	aes_stress	37.000s	2.104ms	50	50	100.00
		aes_sideload	12.000s	429.982us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	419.881us	50	50	100.00
V2	stress_all	aes_stress_all	2.983m	5.048ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	75.293us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	312.559us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	312.559us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	73.247us	5	5	100.00
		aes_csr_rw	8.000s	57.262us	20	20	100.00
		aes_csr_aliasing	4.000s	76.182us	5	5	100.00
		aes_same_csr_outstanding	13.000s	81.456us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	73.247us	5	5	100.00
		aes_csr_rw	8.000s	57.262us	20	20	100.00
		aes_csr_aliasing	4.000s	76.182us	5	5	100.00
		aes_same_csr_outstanding	13.000s	81.456us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.183m	3.304ms	48	50	96.00
V2S	fault_inject	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	169.432us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	486.492us	5	5	100.00
		aes_tl_intg_err	13.000s	810.973us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	13.000s	810.973us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	561.573us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	30.000s	764.650us	50	50	100.00
		aes_stress	37.000s	2.104ms	50	50	100.00
		aes_alert_reset	15.000s	561.573us	50	50	100.00
		aes_core_fi	32.000s	10.206ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	222.696us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	68.171us	50	50	100.00
		aes_stress	37.000s	2.104ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	37.000s	2.104ms	50	50	100.00
		aes_sideload	12.000s	429.982us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	68.171us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	68.171us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	68.171us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	68.171us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	68.171us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	37.000s	2.104ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	37.000s	2.104ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	35.000s	1.380ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	35.000s	1.380ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.007ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	35.000s	1.380ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	561.573us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_ctr_fi	9.000s	294.004us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	35.000s	1.380ms	49	50	98.00
		aes_control_fi	47.000s	10.007ms	279	300	93.00
		aes_cipher_fi	51.000s	10.007ms	337	350	96.29
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	6.200m	82.868ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	99.00	97.49	99.43	95.86	95.60	97.78	98.97	98.17

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
- Test aes_control_fi has 15 failures.
  - 17.aes_control_fi.58673639503948788780280495559469054769074980293221797585084146700017802050818
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:bed04cfd-94c3-490a-8514-786497d07ffe
```
  - 31.aes_control_fi.15198878799349722492126422918336433656167737161572530527163901528929830445205
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job ID: smart:227adb9d-f574-4989-af36-e0685ceb570c
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 5 failures.
  - 166.aes_cipher_fi.31979857680597806667109065778032078174059481568336685232083724978251240773311
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/166.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9213f69a-93d6-4e94-896b-652d55451201
```
  - 168.aes_cipher_fi.71357490840293095750792910115281782617021899659970031759811195748299560962456
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/168.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4735383a-529f-482f-a9cf-a0d6df5a4f46
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 11.aes_cipher_fi.19411857886147471371558007701621976998618225326327710667937413909287407553341
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10023163151 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023163151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 92.aes_cipher_fi.27296467491157876077646819790387217825122998741630563133748295604793329616072
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/92.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014306083 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014306083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.69960557169487886600293275602569485766374671205140031751388674995624828338115
Line 982, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2900356312 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2900356312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.43115185513746248150404009215195371494173045513129598061786043341318667599440
Line 471, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10964884762 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10964884762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 3.aes_control_fi.39040495499525553927727059023750034279044643967614754668762925900095318260871
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006686255 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006686255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_control_fi.108377572534094360068441702794781737377726154374755191084911292225782368647442
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023835366 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023835366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.46789935393576831374338304238425976645365405087092366044674699194688461268206
Line 1778, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3399662303 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3399662303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.40041503638433549354297360572228800807035897941472797943307595508547771238512
Line 1888, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2101100844 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2101100844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.9762526267822681279413880508104607055407733742264307957558445298850886516929
    Line 601, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2196684405 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2196684405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_reseed has 1 failures.
  - 21.aes_reseed.96012964423289733607503216220582890574763663788852777383129576989113116299709
    Line 1040, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_reseed/latest/run.log
```
  UVM_FATAL @ 324655517 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 324655517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:40) [aes_reseed_vseq] Check failed request_seen | finished_all_msgs == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 0.aes_reseed.30478120112287548117092581568883502725052010704348122870933603140214902736889
    Line 2860, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_reseed/latest/run.log
```
  UVM_FATAL @ 106911054 ps: (aes_reseed_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen | finished_all_msgs == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 106911054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 18.aes_fi.63974537021841409904528013375069936390402577444640031978619308621002520630504
    Line 4012, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/18.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 10822869 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 10812869 PS)
  UVM_ERROR @  10822869 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  10822869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 40.aes_core_fi.26103288134793972009361436501178725799265239950011888597671613284443640912255
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10205663869 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10205663869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```