AES/UNMASKED Simulation Results

Thursday May 18 2023 07:04:58 UTC

GitHub Revision: `ac0bef2ce`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2907120974

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	76.857us	1	1	100.00
V1	smoke	aes_smoke	4.000s	99.108us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	92.599us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	95.743us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	509.997us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	1.717ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	194.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	95.743us	20	20	100.00
		aes_csr_aliasing	7.000s	1.717ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	99.108us	50	50	100.00
		aes_config_error	5.000s	917.013us	50	50	100.00
		aes_stress	36.000s	1.934ms	50	50	100.00
V2	key_length	aes_smoke	4.000s	99.108us	50	50	100.00
		aes_config_error	5.000s	917.013us	50	50	100.00
		aes_stress	36.000s	1.934ms	50	50	100.00
V2	back2back	aes_stress	36.000s	1.934ms	50	50	100.00
		aes_b2b	11.000s	592.691us	50	50	100.00
V2	backpressure	aes_stress	36.000s	1.934ms	50	50	100.00
V2	multi_message	aes_smoke	4.000s	99.108us	50	50	100.00
		aes_config_error	5.000s	917.013us	50	50	100.00
		aes_stress	36.000s	1.934ms	50	50	100.00
		aes_alert_reset	5.000s	193.203us	50	50	100.00
V2	failure_test	aes_config_error	5.000s	917.013us	50	50	100.00
		aes_alert_reset	5.000s	193.203us	50	50	100.00
		aes_man_cfg_err	4.000s	59.227us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	167.929us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	372.692us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	193.203us	50	50	100.00
V2	stress	aes_stress	36.000s	1.934ms	50	50	100.00
V2	sideload	aes_stress	36.000s	1.934ms	50	50	100.00
		aes_sideload	6.000s	253.941us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	173.114us	50	50	100.00
V2	alert_test	aes_alert_test	4.000s	64.698us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.056ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.056ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	92.599us	5	5	100.00
		aes_csr_rw	4.000s	95.743us	20	20	100.00
		aes_csr_aliasing	7.000s	1.717ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	80.006us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	92.599us	5	5	100.00
		aes_csr_rw	4.000s	95.743us	20	20	100.00
		aes_csr_aliasing	7.000s	1.717ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	80.006us	20	20	100.00
V2		TOTAL			491	491	100.00
V2S	reseeding	aes_reseed	39.000s	2.765ms	49	50	98.00
V2S	fault_inject	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	801.566us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.356ms	5	5	100.00
		aes_tl_intg_err	6.000s	677.155us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	677.155us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	193.203us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	99.108us	50	50	100.00
		aes_stress	36.000s	1.934ms	50	50	100.00
		aes_alert_reset	5.000s	193.203us	50	50	100.00
		aes_core_fi	41.000s	10.002ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	78.162us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	36.000s	1.934ms	50	50	100.00
		aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	36.000s	1.934ms	50	50	100.00
		aes_sideload	6.000s	253.941us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	79.539us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	36.000s	1.934ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	36.000s	1.934ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	409.937us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	409.937us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	16.442ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	409.937us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	193.203us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_ctr_fi	4.000s	59.078us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	409.937us	50	50	100.00
		aes_control_fi	48.000s	15.783ms	281	300	93.67
		aes_cipher_fi	50.000s	16.442ms	319	350	91.14
V2S		TOTAL			930	985	94.42
V3		TOTAL			0	0	--
		TOTAL			1527	1582	96.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	12	100.00
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.52	94.43	98.77	93.74	97.72	91.11	98.26	92.90

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 10 failures.
  - 3.aes_control_fi.2746760429
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:07f4e76c-9fe2-42df-a575-ea0169ea80f1
```
  - 27.aes_control_fi.3996882795
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job ID: smart:8d6db2ef-fdd3-4063-af2a-2149292d95d7
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 17 failures.
  - 3.aes_cipher_fi.3637481612
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3884fc68-2e66-4192-8257-af17df469b08
```
  - 40.aes_cipher_fi.120620112
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b562326c-756d-4bb4-966b-d497c8199dd8
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 40.aes_ctr_fi.2051968564
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_ctr_fi/latest/run.log
```
  Job ID: smart:6170a466-1c8a-4203-8300-672d95b710a8
```

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:

Test aes_cipher_fi has 14 failures.

6.aes_cipher_fi.3002002263
Line 275, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10126527210 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10126527210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_cipher_fi.65814373
Line 280, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10013519513 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013519513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:

Test aes_control_fi has 9 failures.

47.aes_control_fi.1338988870
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_control_fi/latest/run.log

  UVM_FATAL @ 10007194901 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007194901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

98.aes_control_fi.4176430302
Line 270, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/98.aes_control_fi/latest/run.log

  UVM_FATAL @ 10014424455 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014424455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

57.aes_core_fi.1170159992
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_core_fi/latest/run.log

  UVM_FATAL @ 10008821909 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008821909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

61.aes_core_fi.1524928313
Line 271, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log

  UVM_FATAL @ 10002298997 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002298997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # * has 1 failures:

Test aes_reseed has 1 failures.

22.aes_reseed.3169349246
Line 1563, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_reseed/latest/run.log

  UVM_FATAL @  10400317 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
            TEST FAILED MESSAGES DID NOT MATCH
  
                 0 b3      6e      a6      0
                 1 00      d3      2b      0

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 33.aes_core_fi.3996190755
    Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10046139349 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046139349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```