AES/UNMASKED Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	74.158us	1	1	100.00
V1	smoke	aes_smoke	9.000s	687.742us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	9.000s	86.742us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	71.445us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	20.000s	3.319ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	180.917us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	9.000s	60.624us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	71.445us	20	20	100.00
		aes_csr_aliasing	6.000s	180.917us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	687.742us	50	50	100.00
		aes_config_error	5.000s	144.909us	50	50	100.00
		aes_stress	9.000s	60.457us	50	50	100.00
V2	key_length	aes_smoke	9.000s	687.742us	50	50	100.00
		aes_config_error	5.000s	144.909us	50	50	100.00
		aes_stress	9.000s	60.457us	50	50	100.00
V2	back2back	aes_stress	9.000s	60.457us	50	50	100.00
		aes_b2b	12.000s	97.539us	50	50	100.00
V2	backpressure	aes_stress	9.000s	60.457us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	687.742us	50	50	100.00
		aes_config_error	5.000s	144.909us	50	50	100.00
		aes_stress	9.000s	60.457us	50	50	100.00
		aes_alert_reset	4.000s	89.171us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	113.891us	50	50	100.00
		aes_config_error	5.000s	144.909us	50	50	100.00
		aes_alert_reset	4.000s	89.171us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	112.798us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	205.109us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	89.171us	50	50	100.00
V2	stress	aes_stress	9.000s	60.457us	50	50	100.00
V2	sideload	aes_stress	9.000s	60.457us	50	50	100.00
		aes_sideload	8.000s	297.902us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	128.516us	50	50	100.00
V2	stress_all	aes_stress_all	41.000s	5.346ms	8	10	80.00
V2	alert_test	aes_alert_test	8.000s	58.071us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	20.000s	608.701us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	20.000s	608.701us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	9.000s	86.742us	5	5	100.00
		aes_csr_rw	8.000s	71.445us	20	20	100.00
		aes_csr_aliasing	6.000s	180.917us	5	5	100.00
		aes_same_csr_outstanding	9.000s	138.252us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	9.000s	86.742us	5	5	100.00
		aes_csr_rw	8.000s	71.445us	20	20	100.00
		aes_csr_aliasing	6.000s	180.917us	5	5	100.00
		aes_same_csr_outstanding	9.000s	138.252us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	8.000s	274.269us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	104.604us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.064ms	5	5	100.00
		aes_tl_intg_err	9.000s	483.889us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	483.889us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	89.171us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	687.742us	50	50	100.00
		aes_stress	9.000s	60.457us	50	50	100.00
		aes_alert_reset	4.000s	89.171us	50	50	100.00
		aes_core_fi	25.000s	10.005ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	10.000s	147.787us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	52.651us	50	50	100.00
		aes_stress	9.000s	60.457us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	60.457us	50	50	100.00
		aes_sideload	8.000s	297.902us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	52.651us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	52.651us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	52.651us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	52.651us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	52.651us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	60.457us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	60.457us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	117.052us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	117.052us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.003ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	117.052us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	89.171us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_ctr_fi	14.000s	96.861us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	117.052us	50	50	100.00
		aes_control_fi	49.000s	32.837ms	282	300	94.00
		aes_cipher_fi	46.000s	10.003ms	332	350	94.86
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.717m	3.239ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	97.65	94.69	98.83	93.76	97.64	91.11	98.66	97.36

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test aes_cipher_fi has 6 failures.
  - 7.aes_cipher_fi.80204911736905144573856531722949512421557233164286260439845585755190388065157
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ee957d61-591f-4562-80a3-066ac14d7ff8
```
  - 203.aes_cipher_fi.94677266760940707866974402763333709550449287564777527250600629188205889984783
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/203.aes_cipher_fi/latest/run.log
```
  Job ID: smart:edd19cce-a9a6-4f1f-b123-f620517625c1
```
  - ... and 4 more failures.
- Test aes_control_fi has 9 failures.
  - 45.aes_control_fi.74013123250053128446847827246616077591095664414661138714016529567373609757540
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:ded5b2bb-89ee-48ed-ab0f-cc9207d07da7
```
  - 75.aes_control_fi.10491509937356247891458816224284844700999970533950070835618394088004977948319
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  Job ID: smart:6732edc2-7cab-48da-8dd2-b884cbdf35c7
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 22.aes_cipher_fi.75222781850834106140270704063386355014694620990185459209310783677246477091135
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011410389 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011410389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.aes_cipher_fi.4418813313922489788955508020791463982123907068674553369239370164762317018780
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/94.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008621187 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008621187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 12.aes_control_fi.110029575411371624305661460542335110966028607100991655347962773459054057271405
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008736763 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008736763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_control_fi.113885227274492836839329073824873561235273849314390319151424326094657958749830
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005911930 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005911930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.4452857541631082315768491690099560386365632765061234272170757168475300291361
Line 1342, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3062371032 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3062371032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.25708100420383557523172718421963213027728040268840220961808330850920456327876
Line 544, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2417451753 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2417451753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 2.aes_core_fi.61333011071291325884612182963611776251431262133812469536904067590432156189191
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011136670 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011136670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_core_fi.48152809637746586138783939315542353181893916627493684185092032644724255770342
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010725086 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010725086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:520) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.7404561787449742268907446326050010540103883413193570922300492402946305606002
    Line 23419, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 528547020 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 528547020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.55168377799589952092688270530888259154536607891701719700658776025626470095163
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22133284 ps: (cip_base_vseq.sv:520) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  22133284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 1.aes_stress_all.78944068337582540089928503648087682278335379501234308165568514082202425229622
    Line 92574, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 371218642 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 371208642 PS)
  UVM_ERROR @ 371218642 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 371218642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.12082685765005091339649180063512914500387111152573159247115850718483427250219
    Line 644, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 248198344 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 248198344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.51962529919054459933673221747142198335493938652446718861591803509680785521678
    Line 307, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  33698958 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  33698958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.29528884578543946789790428563530837691679884852520239817994118905417526622144
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10041862585 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041862585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```